Serial Parallel Multiplier Design in Quantum-dot Cellular Automata

Transcription

1 Serial Parallel Multiplier Design in Quantum-dot Cellular Automata Heumpil Cho and Earl E. Swartzlander, Jr. Application Specific Processor Group Department of Electrical and Computer Engineering The University of Texas at Austin Austin, TX USA 1 Application Specific Processor Group

2 Outline Motivation Quantum-dot Cellular Automata Serial Multiplier Designs in QCA Conclusions 2 Application Specific Processor Group

3 Motivation Quantum-dot Cellular Automata (QCA) Alternative to Transistor Technologies Avoids High Power Consumption Due to Leakage Currents Quantum-dot Cellular Automata (QCA) Emerging Nanotechnology for Electronic Circuits Introduced in 1993 Freedom from Complicated Physics High Density, Low Power Consumption, and Fast Some Experimental Devices Have Been Created Several QCA Circuits Have Been Proposed Ripple Carry Adders, Barrel Shifters, and Memories Complex Designs Rare Key Characteristics Inverters and 3-Input Majority Gates Interconnect Consumes Time and Space Difficult to Estimate Timing Until the Layout is Done Signal Synchronization and Refresh Wires Act as Latches Best for Pipeline Architectures Without Feedback 3 Application Specific Processor Group

4 QCA Technology Basic Quantum-dot Cell Square Nanostructure Each Cell Has Four Quantum Dots Can Possess a Single Electron per Dot Charged With Two Electrons Two Polarizations are Possible by Coulombic Repulsion Regular cells Quantom-dot Electron Tunnel Junction P=+1 (Binary 1) P=-1 (Binary ) 4 Application Specific Processor Group

5 QCA Technology Signal Propagation Main Roles of Cells Computation, Storage, and Communication Wire Dominant Design Series of QCA Cells Act Like a Wire Propagate the Signal Clock Zones Four Clock Phases Control the Signal Flow Cells Are Refreshed on Every Cycle 5 Application Specific Processor Group

6 QCA Technology Fundamental Gates Inverter Conventional Gate 3-Input Majority Gate M ( a, b, c) = a! b + b! c + c! a 2-Input AND/OR Gate Implemented by Setting One Input to a Constant a! b = M ( a, b,) a + b = M ( a, b,1) 6 Application Specific Processor Group

7 QCA Technology Multi-Layer Wire Crossovers Use Several Layers for Crossovers 3D Structure Pros and Cons + Area Efficient Design Manufacturability Issues Structure Layout Application Specific Processor Group

8 QCA Technology QCA Circuit Design Rules Cell Size Set at 2nm Width and Height: 18nm Quantum-dot Diameter: 5nm Cell Center-to-Center Spacing: 2nm Size Limit on Cells Per Clock Zone Limit: 15 Cells Proper Propagation Delay and Reliable Signal Transmission Freedom for Routing and a Reasonable Clock Zone Size Minimum Separation of Two Different Wires The Width of Two Cells Clock Increment Rule Increment the Clock Zone at the Clock Arrangement Positions 8 Application Specific Processor Group

9 Serial Parallel Multiplier Designs in QCA Multiplier Design Issues A Parallel Multiplier is a Very Complex Circuit Complex Circuits Often Incur Significant Delay Simple Structure is Desirable Serial-Parallel Multiplier Design Selected Filter Design Methodology is Used 9 Application Specific Processor Group

10 Algorithmic Design FIR Filter Design Example Delay Operator: Z -1 Z x = x Z = Z Z! 1,! n! 1! n + 1 i i! 1 Filter Equation y = b x + b x + b x + L+ b x + b x i i 1 i! 1 2 i! 2 N! 2 i! N + 2 N! 1 i! N + 1 " # = = = $ % & ' N! 1 N! 1 N! 1! k! k ( bk xi! k ( bk Z xi ( bk Z xi k = k = k = Z -1 Z -1 x i y i Application Specific Processor Group

11 Pipelined FIR Filter Network Pipelined FIR Filter Output (Right-to-Left Structure) " " ( ## = Z b Z + Z $ b Z + + Z b Z )% x $ % & & '' !! ( N! 1)!! ( N! 2)! $ N! 1 N! 2 L % i N N N!!! 2!( N! 1) 2!( N! 2) 2 N! 1 i N! 2 i L i = Z b Z x + Z b Z x + + Z b x N! 2 N! 2 N! 1 "! k # ( k k = = Z $ b Z % x & ' = Z y i i Z -3/2 Z -3/2 b N-2 x i Z -N/2 y i Z -1/2 + Z -1/2 + + Z -1/2 11 Application Specific Processor Group

12 Redirected FIR Filter Network General Structure (Right-to-Right Structure) Z -1 Z -1 x i Pipelined Structure Z -1/2 Z -1/2 Z -1/2 + + Z -1/2 + Z -1/2 Z -1/2 y i y i " # Z y Z b Z x & ' x i 1 1!! N! 1 2 2! k i = $ ( k % i k = 1 1 k k! N! "!! # = Z $ ( bk Z Z % x & k = ' 1 1 k k! N! "!! # = Z $ ( Z bk Z % x & k = ' i i 12 Application Specific Processor Group

13 Multiplication Signal Flows Unsigned Number Multiplication Bit Product Matrix and Signal Flow of Right-to-Left Structure X a 3 a Time a 3 a a 3 a a 3 1 a a 3 a a 3 a a 3 a a 3 a a 3 a p 7 p 6 p 5 p 4 p 3 p 2 p 1 p p 7 p 6 p 5 p 4 p 3 p 2 p 1 p p 7 S t e p t 13 t 12 t 11 t 1 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t t -1 t -2 t -3 Bit Product Matrix and Signal Flow of Right-to-Right Structure X a 3 a Time t 12 t 11 t 1 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t t -1 t -2 t -3 p 1 a p a p 7 p 6 p 5 p 4 p 3 p 2 p 1 p p 7 p 6 p 5 p 4 p 3 p 2 a 3 a a 3 a 3 a a 3 a 3 a a 3 a a 3 a a 3 a S t e p 13 Application Specific Processor Group

14 Network Diagrams-I Right-to-Left Carry Shift Multiplication (CSM) Z -7/4 Z -7/4 Z -3N/4 p + + i Z -3/4 Z -3/4 + Z -3/4 + Z -1 Z -1/4 Z -1/4 Right-to-Left Carry Delay Multiplication (CDM) Z -3/2 Z -3/2 Z -N/2 p i Z -1/2 + Z -1/2 + + Z -1/2 Z -1 Z -1 Z Application Specific Processor Group

15 Network Diagrams-II Right-to-Right Carry Shift Multiplication (CSM) Z -1/4 Z -1/4 Z -1 + Z -3/4 + + Z -3/4 + Z -3/4 Z -3/4 p i Z -1/4 Z -1/4 Right-to-Right Carry Delay Multiplication (CDM) Z -1/2 Z -1/2 Z -1/2 + + Z -1/2 + Z -1/2 Z -1/2 p i Z -1 Z -1 Z Application Specific Processor Group

16 QCA Multiplication Diagrams Multiplication Networks for QCA One Clock Zone Delay: D -1 (D -4 =Z -1 ) Filter Network Transformation Using D Operators D -6 D -6 D -1 D -1 D -1 D -1 D -1 D -2N-2 p i D -2 + D D -2 D -2 D -2 D -1 D -1 D -1 D -1 D -1 D D -2 + D -2 D -4 p i 16 Application Specific Processor Group

17 Right-to-Left Networks Equations! 7 j! 2! 3! 1 ( (! 1) ( + 1) ) ( bjai! 7 j! 2 s( i! 3)( j! 1) c( i! 1)( j+ 1) )! 6 j! 2! 2! 4 ( (! 1) ) ( bjai! 6 j! 2 s( i! 2)( j! 1) c( i! 4) j) ( s, c ) = Addition b D a, D s, D c ij ij j i i j i j = Addition,, ( s, c ) = Addition b D a, D s, D c ij ij j i i j ij = Addition,, CSM Network CDM Network D -7 D -7 D -1 D -6 D -6 D -1 D -1 D -1 D -1 D -1 D -1 D -1 D -1 D -1 D -3N-2 p i D -3 + D D -3 + D -4 D -2N-2 p i D -2 + D D -2 D -1 D -1 D -4 D -4 D Application Specific Processor Group

18 Right-to-Right Networks Equations CSM Network! j! 2! 3! 1 ( ( + 1) (! 1) ) ( bjai! j! 2 s( i! 3)( j+ 1) c( i! 1)( j! 1) )! 2 j! 2! 2! 4 ( ( + 1) ) ( bjai! 2 j! 2 s( i! 2)( j+ 1) c( i! 4) j) ( s, c ) = Addition b D a, D s, D c ij ij j i i j i j = Addition,, ( s, c ) = Addition b D a, D s, D c ij ij j i i j ij = Addition,, CDM Network D -1 D -1 D -1 D -2 D -2 D -1 D -1 D -1 D -1 D -1 D -1 D -1 D -1 D -1 D -4 + D D -3 + D -3 D -5 p i D D -2 + D -2 D -4 p i D -1 D -1 D -4 D -4 D Application Specific Processor Group

19 Multiplier Block Diagrams Nominal Design Right-to-Right CSM Modified Design (serial-in) (serial-in) FA FA FA FA FA FA FA FA Right-to-Right CDM p i (serial-out) p i (serial-out) (serial-in) (serial-in) FA FA FA FA FA FA p i (serial-out) p i (serial-out) 19 Application Specific Processor Group

20 4-bit and 32-bit CSM Layouts 2 Application Specific Processor Group

21 4-bit and 32-bit CDM Layouts 21 Application Specific Processor Group

22 4-bit CSM and CDM Simulation Results CSM Results CDM Results 22 Application Specific Processor Group

23 Carry Shift Multipliers Size Complexity Area Latency CSM-4 57 cells 1.4 µm x.61 µm 1.25 clocks CSM-8 1,11 cells 1.93 µm x.61 µm 1.25 clocks CSM-16 2,43 cells 3.67 µm x.61 µm 1.25 clocks CSM-32 4,299 cells 7.24 µm x.67 µm 1.25 clocks CSM-64 9,579 cells 14.3 µm x.85 µm 1.25 clocks 23 Application Specific Processor Group

24 Carry Delay Multipliers Size Complexity Area Latency CDM-4 46 cells 1.5 µm x.47 µm 1 clock CDM-8 93 cells 2.12 µm x.47 µm 1 clock CDM-16 1,999 cells 4.19 µm x.47 µm 1 clock CDM-32 4,575 cells 8.47 µm x.65 µm 1 clock CDM-64 11,264 cells 16.8 µm x.95 µm 1 clock 24 Application Specific Processor Group

25 Comparison of Different Multipliers Multiplier Comparisons Delay: CSM=1.25 clocks, CDM=1 clock Complexity Area Number of QCA cells Size (um^2) CDM CSM Word size (bits) CDM CSM Word size (bits) 25 Application Specific Processor Group

26 Conclusions Summary Serial Parallel Multiplier Architecture Simple Structure Chosen for Wire Delay Minimization Regular Cells for Design Reuse Optimized to Minimize Latency Serial Parallel Multiplication Network Based on Filter Network Example Derived the Equations and Network Graph Designed Two Serial Parallel Multipliers Carry Shift Multiplier and Carry Delay Multiplier Contributions Extended QCA Circuit Designs to Multiplication Explored Various Serial Parallel Multiplication Algorithms 26 Application Specific Processor Group

27 QUESTIONS??? 27 Application Specific Processor Group