NOVEL QCA CONTROL GATE AND NEW DESIGNING OF MEMORY ON THE BASIS OF QUANTUM DOT CELLULAR AUTOMATA WITH MINIMUM QCA BLOCKS

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1 Indian J.Sci.Res. 2(1) : , 2014 ISSN : (Online) ISSN: (Print) NOVEL QCA CONTROL GATE AND NEW DESIGNING OF MEMORY ON THE BASIS OF QUANTUM DOT CELLULAR AUTOMATA WITH MINIMUM QCA BLOCKS M.H.TAJARROD a 1 AND M.ARJOMANDI b a Department of electronics, Islamic Azad University, Tabriz branches, Tabriz, Iran. b Department of engineering, MSC student of electronics, Azad University, Fasa branches, Fasa, Iran. ABSTRACT New technology of designing quantum-dot cellular automata circuits (QCA) has been studied in previous decades because of its tiny dimensions, high speed and very low power consumption. This technology has proved its ability of using the quantum knowledge in constructing logical devices so that considered as a suitable substitute for CMOS technology. In this paper, a new control gate (4-status gate) is designed on the basis of QCA technology. This special gate establishes four logical functions, 3-inputs AND and OR, OR in AND binary and AND in OR binary. These functions are very useful in designing digital circuits. By using them, logical circuits can be designed in minimum number of QCA blocks and less number of gates and consequently higher speed and lower consumable power. Also, a novel circuit and new formulation structure is presented for memory cell. In this formulation, the memory cell structured in a single layer, with 74 QCA cells, by using the new 4-status gate which is introduced in this paper. At last, correctness and completeness of design is experimentally validated by simulating it with QCA-Designer tools. KEY WORDS : Quantum- Dot Cellular Automata, Qca, Base Cell, Majority Gate, Circuit's Formulation, Memory. In the last three decades, smaller scale in designing VLSI systems with high speed and low power achieved by the use of CMOS technology. But, decrease in transistors size to nanometer scale causes unwilling changes in system behavior. Exploitation of symmetry in logic systems is a solution to solve this problem [1, 2]. For increasing the efficiency of logic systems, new nanotechnology must be used in their structures. There are various methods for designing Nano electronics. But the most useful item is Quantum- Dot Automata that briefly called QCA (Quantum- Dot Cellular Automata). QCA is a new method that not only gives us a chance to design in Nano-scale but also provides new ways in calculating and transforming data [3, 4]. The most basic QCA circuits is majority gate that shows significant performance in designing QCA circuits. Of course some of these items are not proved to be true [5, 6]. The base of QCA function is encoding binary information on the basis of electron's position in the Quantum cell [7] and "auto cells" comes from the position of a given cell in a special time depends on the neighbor s Quantum cell in the previous time period [8,9]. By increase in switching speed, this technology makes a better frequency answers in electronic circuits. Also it decreases the consumable power slightly. In addition, it can design denser circuits to 1012 devices/cm2 [10-12]. In this paper, first the function of Quantum dot is described and then a new control gate (4status gate) will be introduced and its function will be explained and demonstrate the validation of this gate with cells energy calculation. In addition, the method of creating basic gates and transforming crossover routes into a single layer and a new method in transforming input with it's NOT will be presented. The memory circuits with the new 4status gate and the cell formulation for presenting this circuit will be introduced later. Then benefits of this circuit in contrast with previous ones will be discussed. At the end, with simulation 1 Corresponding author of this circuit by the use of QCA-designer, the conclusion will be surveyed and their truth will be proved. DESCRIBING THE USE OF QUANTUM- DOT CELL IN BASIC BLOCK'S DESIGN: Structure of the auto cells in QCA is very exclusive. Each cell consists of 4 places for Quantum-dot and two trapped electrons that are shown in Fig. 1. Electrons cannot move between cells but they can tunnel through them. Columbic interaction between electrons causes the diagonal order in cells and this power influences the neighbor cells to follow those electrons in their configuration. As it's seen in Fig. 1, there are two types of electrons placement. In the left (polarization +1) logic is 1 and in the right (polarization -1) logic is 0. Fig. 1: QCA Cell. In a situation that cell orients in 90-degree (Fig. 2), when electrons are in horizontal state the polarization is +1 and when they are in vertical state, the polarization is -1. Fig. 2: oriented 90-degree cells polarization Because of columbic interaction between electrons, neighbor electrons organize like figure3- and in 90 degree state they appears like Fig. 3-b.

2 contrasts with input cell. By the use of this process, The NOT of input can be attained (see Fig. 8). Fig. 3: transforming line. a) Common line. b) oriented 90- degree line When electrons in a cell switch their state by the force of potential, because of columbic interaction between cell's electrons of next cell also change in the same way. For example in Fig. 4 electrons of cells switch from left side to right side (Fig. 4). The columbic effect switches cell 2 to cell4 sequentially. Fig.6: crossover transforming line The oriented 90-degree cells not only make a transforming input cellular line but also it creates input NOT. It is worthwhile to mention that using this transforming line also provides a possibility of formulating cell in just one layer. Fig. 4: columbic effect in switching 1. Designing basic gate by the use of QCA cell 1.1. AND and OR gates When five cells get together like a cross, the state of cell 5 (output) depends on the sum of colonial power of three behinds cells. So, if two of three input cells situate in polarization (+1) or (-1), the output cell has the same situation. This block with five cells is mentioned as a base block of majority gate. The output function is seen in equation 1. In equation 1 if c= -1 (logic zero) the AND gate is created and if c= +1 the OR gate can be implemented. Fig.7: oriented 90-degree transforming line 1.2. Designing 4-status gate (new control gate) After lots of research, we design a new gate that provides significant properties in designing circuits. The construction of this new gate (control gate) is shown in Fig. 6. Fig. 5: basic gate DESIGNING INPUT LINE TRANSFORMING: When using the oriented 90-degree cells, they are situated alternately in polarization +1 and -1 (Fig. 3-b). Therefore, for extracting a transforming line it is necessary to consider that horizontal cell must be placed under the cell by individual interval with regard to input cell or on the cell by couple interval. Otherwise, the horizontal cell polarization (1) Fig. 8: 4 status gate (new control gate) According to columbic interaction between electrons, the output of this gate obtains from equation2: (2) This gate provides four important logical functions: a) 3inputs AND Indian J.Sci.Res. 2(1) : ,

3 In 4status gate if A input polarization fix to -1 (logic zero) then according to formula 3, the output will be AND operation of 3 inputs. (3) b) 3inputs OR In the 4status gate if A input polarization fix to +1 (logic1) then according to formula 4 the output will be OR operation of 3 inputs. (4) c) A(B+C) By fixing one of the inputs B, C or D to logic zero, the gate output is in accord with formula5. (5) d) (A+BC) By fixing one of the inputs B, C or D to +1(logic 1), the gate output is in accord with formula5. (6) Gates that are achieved according to formula 3 and 4, are basic 3inputs AND and 3inputs OR gate. These gates have large application in logical circuits and may decrease the number of QCA cells in construction of electronic parts. Each achieved gate according to formula 5 and 6 have significant and potential application in construction of logic circuits. For instance, function 4, has a very important role in construction of a memory cell and increases the speed of it, lessens consumable power, decreases the number of used gate in memory cell, and causes very low volume in implementation. The application of this memory cell is as follows. In this formula, U is the potential energy, K is coulomb's constant, Q is electron's electric charge and R is the distance between two electric charges. By setting value for K and Q in this formula the fixed value will be attained. When the inputs state applied, we have to calculate the effect of inputs electron's charges in neighbor's cells for each polarization (+1,-1) of them and of course the polarization of the neighbors that has lower columbic interaction with inputs is the stable state. By considering the existing 4 status inputs in this gate, 16 different states of inputs will be obtained. The truth of one state will be validated as follows. Similarly, the truth of all these states can be calculated. Figure 9 shows 4-state control gate marking each cells. Be assumed that inputs are obviously the cells number 5,6,7 polarization are similar to inputs A,B and D sequentially. For other cells and output we have to calculate all neighbors' columbic interaction. table 1 represented potential energy in output in each polarization and the stable polarization. Comparing these two values shows that arrangements of electron's charges are more stable in state 1 because of lower potential energy. These calculations are done for cell8, 9 and 10and the results are presented below. CALCULATING ENERGY IN GATE: As it is seen in figure 6, 4-status control gate has four inputs that is built just by ten cells in a way that it can be used to organizing some logical functions. All cells are similar. They are in a square shape with 18*18 and there is a space of 2nm between each two cells. The existing holes are electron's position. For more stability in cells, they are placed in such ways that suffer less energy. The potential energy between two electrons can be calculated by equation 7 (7) Fig.9: 4-state control gate marking The other input states (15 other states) can be computed in the same way. According to these calculations, the truth of the control gate's operation is proved. So, various functions can be created by a control input. In the new section, we will study the effects of this gate in designing memories. Then a new memory model with minimum number of gates and cells will be presented. Indian J.Sci.Res. 2(1) : ,

4 table 1: potential energy in gate's cells Cell number Effective cells in Columbic interaction Negative polarization (-1) Positive polarization(+1) Cell 8 2, 6, e e Cell 9 2, 5, e e Cell 10 7, 8, 9, e e Cell F 7, 9, e e Stable state Inputs value: In this table the calculation of cells 5,6 and 7 disregarded because their polarization are similar to inputs A,B and D sequentially. DESIGNING (NEW) MEMORY CELL CIRCUITS: The primary structure of a logic circuit memory cell is shown in figure 10. Totally 6 AND gates and 2 NOT gates are used in this design. Constructing this logic circuit by the use of basic QCA gates will be possible if AND and OR gates substitute for logic gate in figure 11 circuit. Fig.11: novel memory cell logical circuit Figure 10 shows the new logic circuit memory cell designed by the use of 4 status gate (presented in this article). As the figure 11 shows, memory cell circuit design with 4 status gate, not only decreases 2 gates in a circuit and design's volume but also increases the function speed of memory cell. Fig.10: primary memory cell logical circuit In this article, a new memory cell is designed on the basis of recently presented control gate that includes lower number of gates. This design consists of two changes; The first change is in the output of memory cell circuit. In the output of figure 7, W/R and S input (with available value in memory cell) gets AND. Consequently, instead of using two AND gates, we can use one AND gate with three inputs. The new presented gate (4 status gate) in this article has proper characteristic for this situation. The next change and the more important one can be applied on memory cell ring. In figure 10, IN input gets AND with the results of AND operation of inputs; W/R and S, and then gets OR with the value of memory cell ring (Q1). This structure (formula 7) is one of the important presented relations in 4 status F = Q 1 + (W/R S) (IN) (7) gate that can construct formula 7 of memory cell circuit in one stage. In formula 7, W/R*S is equivalent to B, IN is equivalent to C and Q1 is equivalent to A in formula Memory circuit's formulation: Memory circuit's order is constructed on the basis of figure 11. It is shown in figure 12. This order consists of two 4 status gates, two base gate (AND two inputs) and a NOT maker. it is designed in compliance with the use of four cells to change clock pulse and a distance of two cells between transforming lines in order to be organized without errors in practical designs while these notes was not followed in previous works [13]. SIMULATION RESULTS QCA Designer is used for the proposed memory cell formulation (figure13). If S be logical zero the output results are zero too and if S be logical one, the results correspond to figure 13. As it is shown in this figure, When WRITE is active, in any situation on last WRITE edge, the input is saved in the memory and during the reading function it correctly reaches the output. For example, when clock pulse is active in 2800 to 3500 range, the WRITE command is activated for cell and the input remains on logic 1. Consequently logic 1 stores in the memory. After the activation of READ command in clock pulse the memory value will be read that is logic 1. It can be seen in figure 13. Indian J.Sci.Res. 2(1) : ,

5 CONCLUSION A new control gate (4 status gate) that proposed in this paper is based on Quantum dot cellular automata technology and presents four important (3 inputs) functions, then provided new design for memory cell by the use of 4 status gate. Because of decrease in number of gates and additionally lower volume, it operates with less consumable power and higher speed. The new design is constructed just by the use of 4 gates in one layer and with 71 QCA cells. Clock pulse laws and the rule of two cell interval between transforming lines are obeyed in this formulation in order to be applicable in practical simulation. However, the results can be compared with circuits in previous articles [13] that have 167 cells and disobeyed the clock pulse changes rule. [12] N. Kazemifard, M. Ebrahimpour, M. Rahimi, M. Tehrani, and K. Navi, Performance evaluation of in-circuit testing on QCA based circuits, in: Proceedings of the 6th IEEE East- West Design and Test Symposium, [13] K.Walus, T.J.Dysart, G.A.Jullien, A.R.Budiman, QCADesigner: A Rapid Design and Simulation Tool for Quantum-Dot Cellular Automata,in: Nanotechnology, IEEE Transactions, Volume: 3, Issue: 1, REFERENCES [1] S. Timarchi, K. Navi, Arithmetic circuits of redundant SUT -RNS, IEEE Transactions on Instrumentation and Measurement, doi:1o.1109jtlm [2] A Sabbagh Mollahosseini, K. Navi C. Dadkhah, O. Kavehei, S. Timarchi, Efficient reverse converter design for the new 4-moduli sets {2"-1, 2", 2"+1, 2 2 " +1-1} and {2"-1, 2"+ 1, 2 2 ", 2 2 "+ 1} based on new CRTs, IEEE Transactions on Circuit and Systems, 57 (4) : [3] AO. Orlov, 1. Amlani, G.H. Bernstein, C.S. Lent, G.L. Snider, Realization of a functional cell for quantum-dot cellular automata, Science, 277: [4] P.D. Tougaw, C.S. Lent, Logical devices implemented using quantum cellular automata, journal of Applied Physics, 75 (3): [5] K. Navi, S. Sayed salehi, R Farazkish, M.Rahimi Azghadi, Five-input majority gate, a new device for quantum-dot cellular automata, journal of Computational and Theoretical Nanoscience, 7 (8): [6] M.R Azghadi, O. Kavehei, K. Navi, A novel design for quantum-dot cellular automata cells and full-adders, journal of Applied Sciences, 7 : [7] C.S. Lent and B. Isaksen, "Clocked molecular quantum-dot cellular automata," Electron Devices, IEEE Transactions on, 50 (9): [8] C.S. Lent and P.D. Tougaw, "A device architecture for computing with quantum dots", Proceedings of the IEEE, 85 : 541. [9] T. J. Dysart, "Defect properties and design tools for quantum dot cellular automata", Master's thesis, University of Notre Dame, [10] C. S. Lent and B. Isaksen, "Clocked molecular quantum-dot cellular automata," IEEE Trans. Electron. Devices, 50 (9), [11] J. Timler and C. S. Lent, "Power gain and dissipation in quantumdot cellular automata," J. Appl. Phys., 91(2): Fig.12: memory circuit layout Fig.13: memory cell simulation result Indian J.Sci.Res. 2(1) : ,