BINARY TO GRAY CODE CONVERTER IMPLEMENTATION USING QCA

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1 BINARY TO GRAY CODE CONVERTER IMPLEMENTATION USING QCA Neha Guleria Department of Electronics and Communication Uttarakhand Technical University Dehradun, India Abstract Quantum dot Cellular Automata (QCA) is a nanotechnology which offers an attractive solution to overcome the physical limits that CMOS devices faces during further downscaling of their dimensional sizes. In QCA, the electrons are basically restrained in quantum dots. The fundamental basic gates in QCA are the Majority Gate (MG) and the*inverter. Further downscaling of the dimensions of CMOS devices is more and more challenging, as reduction in feature size of CMOS devices has reached to its feature size limit. So we use QCA which provides powerful features such as higher packaging density, reduced area, much lower power dissipation and higher switching speeds at nanometer scale. QCA designs new logic circuits which are translations of standard logic devices. Here in this paper we proposed QCA implementation of binary to gray code converter. Keywords coulombic interaction; downscaling; majority gate; feature size; quantum dots; quantum-dot cellular automata (QCA). I. INTRODUCTION QCA is an evolving nanotechnology and has capability to develop digital circuits with higher packaging density, reduced area, much lower power dissipation, and higher switching speed. QCA results in ultra-dense, high-performance digital devices as it works at nanometre scale. It is used to design new logic circuits which are basically a translation of standard logic devices. Dimensional scaling of CMOS based logic circuits is approaching its limit of feature size reduction. Further reducing the size of CMOS based circuits result in many problems and doesn t produce the necessary output required. It is believed that the physical size and the corresponding performance of the various circuits based on CMOS technology is close to the reaching limit. Alternatives to conventional CMOS technology is QCA which provides higher density, lower dissipation of power, higher clock frequency and better output results are needed. Quantum Dot Cellular Automata (QCA) technology is explored and introduced. When a new technology is introduced, new design principles are also necessary to consider. The design nature of QCA is not very complicated, instead it is simple than the conventional technologies therefore presents itself as an attractive option in designing of new circuit layouts. New ideas are always required for converting standard logic units into new QCA designs so that the best output results can be obtained. QCA technology enhances the system performance by avoiding the problem associated with information loss and interconnect delays. In QCA, cells perform both the function of logic structures and interconnections. It means that QCA cell can be used as a wire and it can also be used to perform any desired logic functions. Wire crossover defines a very important aspect of designing logics which are systematic in nature, so its implementation should be done properly. In this brief, we proposed the implementation of lower area, higher speed and higher clock frequency binary to gray code converter using QCA technology. Here we also shows the EX-OR gate implementation using QCA. The remaining part of the paper is organized as follows: Section II involves the information regarding each and every aspect of QCA. It involves information about what QCA is, how the QCA cell works and all the necessary details regarding QCA basics. Section III includes proposed work; this section shows the proposed schematics of proposed designs. Section IV includes results, which are the simulation results and finally in last section; that is, Section V, conclusion and future scopes are presented. This section includes future aspects of QCA. II. BACKGROUND QCA device is a nanostructure whose fundamental unit is QCA cell. QCA cell structure and cell polarization is shown below in fig 1). According to the figure, in a QCA cell there are four quantum dots that are present within the corners of a square where two electrons occupies opposite locations in the quantum dots [9]. These quantum dots are the sites where the electrons are capable for tunnelling between them. (a) Fig. 1) (a) QCA Cell structure and (b) Different Polarizations QCA Cell (b)

2 In a QCA cell, diagonal positions of quantum dots are occupied by the two electrons, which are known as antipodal sites. The electrons occupy diagonal position into the quantum dots, so that there is minimum Coulombic repulsion force. The circuits implemented using QCA are based on Columbic interactions between the cells which accomplish logical operation and transfer of data. Movement of data within the cells are through coulombic interactions, not through transfer of charge between the cells. In QCA the locality of electrons in the quantum dots are used for determining the logic levels unlike in CMOS technology where voltage and currents levels are used. The arrangement of electrons in the cell denotes the cell polarizations (P). The cell polarizations are used to encode the binary information. Polarization = +1, represents binary logic level 1 and Polarization = -1, represents binary logic level 0. Polarization denotes only electron location doesn t indicate dipole moment of the cell. In QCA, majority gate with 3 inputs, inverter, and wire are fundamental logic primitives of QCA, shown in fig. 2), fig. 3), fig.4) below. Majority gate with inverter; that is, MI is generally used as it provides complete functions to realize different QCA designs. crossover design and the second category is multilayer crossover design. The second one; that is, the multilayer crossing is utilized in this paper. In QCA, we design the circuit by proper arrangement of cells with proper clock delays. QCA cells array results in QCA structures. When proper clocking scheme is applied to these QCA structures we obtain QCA logic designs. QCA cell array acts as a Quantum dot Cellular Automata linkage, which is shown above in fig.4). These QCA cells which forms wire, provides a medium for transfer of data based on electrostatic forces. In a QCA design to attain tractable information flow, the cells present in the QCA layout circuits are distributed into Clock Zones. Fig. 2) Majority Gate Fig. 5) Zone Clocking Scheme and Clock Signal Phases input Fig. 3) inverter Fig. 4) QCA Wire output One of the most important features of QCA cell is that it can perform both the functions; that is, it can be used for designing logic structures as well as for interconnections. Wire crossover plays a very important role in designing logics and reducing circuit complexity. There are mainly two categories of crossovers designs in Quantum dot Cellular Automata. First category is coplanar There are four clock zones in QCA cell and each clock zone are associated with four different phases which are Switch phase, Hold phase, Release phase and Relax phase and each phase is repositioned by 90⁰ phase shift. This scheme of distributed clocks is known as Zone Clocking Scheme. QCA design becomes intrinsically pipelined with this zone clocking scheme. Clocking provides a method to synchronize the flow of information in the circuit. During switch phase, from an unpolarized state, a cell is polarized [6] depending on the state of neighbour cell. During the hold phase, cell holds its polarization [6]. QCA cells are unpolarized during release and relax phase, and every zone of clock acts like a D-latch [1]. Each zone in cells performs a specific calculation. Clock zones and clock phases are shown in fig. 5) above. *Majority gate (MG) and inverter are fundamental basic gates present in Quantum dot Cellular Automata technology. With the help of these, any QCA circuit can be design easily. For 3 input majority gate the three inputs are A, B, C and the Boolean operation performed by MG is shown as [1]

technology that is majority gate and inverter. In this design we use 3 EX-OR gates for designing the 4 bit binary to gray code converter. Here we also proposed QCA design for EX-OR gate. A.

3 M (A, B, C) = AB + BC + AC (1) B3 A3 III. PROPOSED WORK Fig. 7) Schematic layout of 4-Bit Binary to Gray Code Converter Here in this paper we presented the QCA implementation of 4- bit binary to gray code converter [7] using the fundamental elements of QCA technology that is majority gate and inverter. In this design we use 3 EX-OR gates for designing the 4 bit binary to gray code converter. Here we also proposed QCA design for EX-OR gate. A. EX-OR gate implementation in QCA EX-OR gate using QCA technology is designed by using 1 OR gate, 2 AND gates, and 1 inverter. The AND gate and OR gate is implemented using majority gate. This EX-OR gate is used in implementation of 4-bit converter [7]. The schematic design is presented below in fig 6). From the figure given below, for the inputs A, B and C the output is out. IV. RESULTS The proposed designs are implemented using the QCADesigner tool. The QCA cells are 18nm high and 18nm wide and the diameter of quantum dot is of 5nm [1]. Layout and Simulation result of EX-OR gate and 4-bit converter are given below in fig. 8), fig. 9), fig. 10), fig. 11), fig.12). Fig.8) QCA Layout of EX-OR Gate Fig. 6) Schematic layout of EX-OR gate B. 4-Bit Binary to Gray Code Converter implementation using QCA The circuit design of 4-bit binary to gray code converter [7] is given below in fig. 7). Here we propose a design using 3 EX- OR gates. In this design we use multilayer crossings instead of coplanar crossover. In this QCA layout design we uses 9 majority gates, 3 inverters and 2 multilayer crossovers. B0 B1 B2 A0 A1 A2 Fig. 9) Simulation Result of EX-OR Gate The layout implementation for EX-OR gate is given above in fig. 8). It shows that the cell count is of 51cells and the area used is 0.08µm 2. 4 clock zones are used or we can say that there is 1 clock delay. This design layout is verified by simulating the design and comparing the simulation results with the truth table of EX-OR gate. The simulation result is shown above in fig. 9). Here, there is 1 clock delay after which the required output is obtained. Here we use exhaustive vector table simulation engine setup [13].

First half consist of inputs from decimal 0-7 and the second half consist of inputs from decimal 8-15. The inputs are applied using the vector table type simulation engine setup [13].

4 Fig. 12) Simulation of Second Half Input of Binary to Gray Code Converter The figures shown above, that is; fig. 11) and fig. 12) are the simulation results of the implemented layout of 4-bit binary to gray code converter [7]. The results are simulated in two halves. First half consist of inputs from decimal 0-7 and the second half consist of inputs from decimal The inputs are applied using the vector table type simulation engine setup [13]. In this setup we can apply the input values according to our requirements. This design layout is verified by simulating the design and comparing the simulation results with the truth table given below in Table I. There is 1 clock delay in the simulation results. Fig. 10) QCA Layout of 4-Bit Binary to Gray Code Converter The layout implementation shown in fig. 10) shows the use of 3 EX-OR gates in realizing this design. The cell count of this design is 225. There are 3 OR gates, 6 AND gates and 3 inverters. So in total there are 9 majority gates in this design. There are 2 multilayer crossovers in this design. This crossover design consists of multiple layers which act as a bridge. The area used by this design is 0.43µm 2. This layout uses 4 clock zones hence there is 1 clock delay. TABLE I. TRUTH TABLE OF 4-BIT BINARY TO GRAY CODE CONVERTER Inputs Outputs B3 B2 B1 B0 A3 A2 A1 A Fig 11) Simulation of First Half Input of Gray to Binary Code Converter

5 we have implemented 4 bit converter in future higher bits inverter with more than 3 input majority gate can be implemented. In future more emphasis will be on interconnects and routing as both are implemented using QCA cells and also requires special precautions while implementing them. It also includes various methods to develop simple as well as complex memories, multipliers and other sequential circuits for fast working and methods to enhance them References Table II given below presents the various parameters of the ex-or gate design and proposed 4-bit binary to gray code converter [7] design in QCA. These parameters are the powerful features of QCA design which results in higher switching speed, lower area, high packaging density and much lower power dissipation. These designs are high performance designs as they are in nanometer scale. Table II given below shows the truth table of proposed 4-Bit binary to gray code Converter [7]. TABLE II. QCA structures SIMULATION PARAMETERS OF PROPOSED DESIGNS Proposed structures Complexity Area Latency Figure EX-OR gate 51 cells 0.08µm 2 1 Fig. 8) 4-Bit Binary to Gray Code Converter 225 cells 0.43µm 2 1 Fig.10) V. CONCLUSION AND FUTURE SCOPE New QCA designs for ex-or gate and 4-bit binary to gray code converter [7] are presented in this paper. Designing the layout circuit and simulating the proposed layouts is done using QCADesigner tool. The output and functionality of these circuits are verified. The proposed circuits are implemented using least number of cells, minimum clock delays. The result shows that the design is area efficient and has lower clock delay. The parameters obtained from the results shows that the area occupied by the 4-bit binary to gray code converter [7] is nm^2, with cell count of 225. The design has 1 clock delay. The results are verified by the truth tables. Here [1] S. Perri, P. Corsoneilo, and G. Cocorullo, Area-Delay Efficient Binary Adders in Quantum dot Cellular Automata, IEEE Transaction on VLSI systems, vol. 22, no. 5, pp , May [2] F. Ahmad, G.M. Bhat, P.Z. Ahmad, Novel Adder Circuits Based on QCA, Circuit and Systems, pp , [3] K. Latha, M.N. Maharshi, Design of adders using Qunatum dot Cellular Automata, IJAET, Sep 2013, ISSN: [4] V. Vankamamidi, F.Lombardi, 2-Dimensional Schemes for Clocking/Timing of Quantum dot Cellular Automata Circuits, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1,pp , Jan [5] H. Cho, E.E. Swartzlander, Adder Designs and Analyses for QCA, IEEE Transaction on Nanotech., vol. 6, no. 3, pp , MAY [6] V. Pudi and K. Sridharan, Low Complexity Design of Ripple Carry and Brent Kung Adders in QCA, IEEE Transaction on Nanotech., vol. 11, no. 1,pp , Jan [7] M.G. Waje, Dr. P.K. Dakhole, Design and Simulation of New XOR Gate and Code converters using QCA with reduced number of wire crossings, 2014 International Conference on Circuit, Power and Computing Technologies [ICCPCT], pp , [8] N. Sonare, S. Meena, A Robust Design of Coplanar Full adder and 4- bit Ripple Carry Adder using QCA, IEEE International Conference On Recent Trends In Electronics Information Communication Technology, India, pp , May [9] G. Khademi, S. S. Fahraj, M. T. Moradgholi, M. Houshmand, Logic Optimization of Quantum dot Cellular Automata Circuits using Ant Colony Optimization, the 22 nd ICEE, pp , May [10] S. Perri, P. Corsonello, New Methodology for the Design of Efficient Binary Addition Circuits in QCA, IEEE Transaction on Nanotech., vol. 11, no. 6, pp , Nov [11] H. Cho, E. E. Swartzlander, Adder and Multiplier Design in QCA, IEEE trans. on Computers, vol. 58, no. 6, pp , June [12] M. B. Tahoori, J. Huang, M. Momenzadeh, F. Lombardi, Testing of QCA, IEEE Transaction on Nanotech., vol. 3, no. 4, pp , Dec [13] QCADesigner Documentation (online). Available at: www. Mina.ubc.ca [14] A. Chaudhary, D. Z. Chen, X. S. Hu, K. Whitton, M. Niemier, R. Ravichandran, Eliminating Wire Crossings for Molecular Quantum dot Cellular Automata Implementation, IEEE Transaction., pp , [15] R.Zhang, K. Walus, W. Wang, G. A. Jullien, Performance Comparision of QCA Adders, IEEE conference on circuit and system, pp , 2005.

DESIGN OF QCA FULL ADDER CIRCUIT USING CORNER APPROACH INVERTER

Research Manuscript Title DESIGN OF QCA FULL ADDER CIRCUIT USING CORNER APPROACH INVERTER R.Rathi Devi 1, PG student/ece Department, Vivekanandha College of Engineering for Women rathidevi24@gmail.com