An Efficient design of Binary comparators in Quantum Dot Cellular Automata

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1 An Efficient design of Binary comparators in Quantum Dot Cellular Automata Dammalapati Dileep 1, Vallabhaneni Ramesh Babu 2 1 PG Scholar, Dept of ECE (VLSI &Amp; ES), V.K.R., V.N.B., & A.G.K. College of Engineering, AP, India, 2 Asst Prof, HOD, Dept of ECE, V.K.R., V.N.B., A.G.K. College of Engineering, AP, India, ledileep@gmail.com, vkrecehod@gmail.com@gmail.com Abstract: Quantum-dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultra dense low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. Nevertheless, since the design of digital circuits in QCA still poses several challenges, novel implementation strategies and methodologies are highly desirable. This paper proposes a new design approach oriented to the implementation of binary comparators in QCA. The comparators proposed here exhibit significantly higher speed and reduced overall area. In recent years the design of logic circuits based on QCA has received a great deal of attention. And special efforts have been directed towards arithmetic circuits, such as adders, multipliers, and comparators. In recent years the design of logic circuits based on QCA has received a great deal of attention. And special efforts have been directed towards arithmetic circuits, such as adders, multipliers, and comparators. This paper focuses on the design of efficient parallel QCA based n-bit full comparators. The main contribution of this paper is the introduction of a novel design methodology that allows low computational time and very compact layouts to be achieved. Keywords. Comparator, Adders, Multipliers. Introduction Quantum-dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultra-dense low-power high-performance digital circuits. QCA cells are used for both logic structures and interconnections that can exploit either the coplanar cross or the bridge technique. As an alternative to CMOS-VLSI, researchers have proposed an approach to computing with quantum dots, the quantum cellular automata (QCA). First proposed 1 in 1994, unlike conventional computers in which information is transferred from one place to another by means of electrical current, QCA transfers information by propagating a polarization state. QCA is based upon the encoding of binary information in the charge configuration within quantum dot cells. Computational power is provided by the Colombia interaction between QCA cells. No current between cells and any power or information is delivered to individual internal cells. Although most molecular electronics schemes focus on charge transfer through a molecule, charge transfer within a molecule offers an alternative physical basis for computation. A purely columbic mechanism for information transmission and processing has been extensively studied in theoretical work on quantum-dot cellular automata (QCA). This work envisions arrays of cells built from quantum dots or (on a molecular scale) from individual redox centres, in which charges move within the cells in response to external electric fields. According to this scheme, there is no need to let charges flow through the cells, computation is a ground-state phenomenon and contacts need only be made to some cells at the edges of the array (minimal interconnect). The local interconnections between cells are provided by the physics of cell-to-cell interaction due to the rearrangement of electron positions. While there is still much work to be done, early experimental results indicate that QCA may be an extremely viable alternative to CMOS. QCA cells and a simple QCA logical device have been successfully fabricated and tested. QCA is a nanostructure having as its basic cell a square four quantum dots structure charged with two free electrons able to tunnel through the dots within the cell. Because of columbic repulsion, the two electrons will always reside in opposite corners. The use of quantum-dots is a promising emerging technology for implementing digital systems at the Nano-scale level. Recently studied computational paradigms for quantum-dot technology include the use of locally connected quantum-dot cellular automata (QCA). This technique is based on the interaction of electrons within quantum dots that take advantage of quantum phenomena; the same phenomena that may prove problematic in future integrated circuit technologies as feature sizes continue to decrease. The potential application in telecommunications technologies of QCA and the proposed devices is widespread and clear. By taking full advantage of the unique features of this technology, we are able to create complete circuits on a single layer of QCA. Such devices are expected to function with ultralow power consumption and very high operating speeds. IJAEM SRC. All rights reserved

2 An Efficient design of Binary comparators in Quantum Dot Cellular Automata Literature Survey In [1] an effort has been made to present the review of the work carried out in QCA till date, from the time of its invention in Shockley s transistor invented in 1952 has shrunk immensely as the years pass by, making the electronic computers very compact and one of the most powerful devices of the century. However advancements in Microelectronics as per Moore's law, face huge technical barriers in the future of transistor based computation due to the limitations posed at the nanoscale size. In view of this the International Technology Roadmap for Semiconductors (ITRS) has indicated several new technologies that are likely to replace the transistor based computation in the near future. Some of these include Resonant Tunnelling Diodes (RTDs), Single Electron Tunnelling (SET), Quantum Cellular Automata (QCA), and Tunnelling Phase Logic (TPL). Among these, QCA seems to be the most promising emerging technology, as a viable alternative to CMOS. Quantum-dot cellular automata (QCA) [2] is an attractive emerging technology suitable for the development of ultra-dense low-power high-performance digital circuits. It achieved speed performances higher than all the existing. QCA adders, with an area requirement comparable with the cheap RCA and CFA demonstrated. The novel adder operated in the RCA fashion, but it could propagate a carry signal through a number of cascaded MGs significantly lower than conventional RCA adders. In addition, because of the adopted basic logic and layout strategy, the number of clock cycles required for completing the elaboration was limited. As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantumdot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always straightforward. The design of ultra-low-power multipliers on quantum dot cellular automata (QCA) nanotechnology, promising very dense circuits and high operating frequencies, using a single homogeneous layer of the basic cells [3]. We construct structures without the earlier noise problems, verified by the QCA Designer coherence vector simulation. Our results show that the wiring overhead of the arithmetic circuits grows quadratically with the operand word length, and our pipelined array multiplier has linearly better performance-area efficiency than the previously proposed serial-parallel structure. Power analysis at the fundamental Landauer s limit shows, that the operating frequencies will indeed be bound by the energy dissipated in information erasure: under irreversible operation, the limits for the clock rates on molecular QCA are much lower, than the switching speeds of the technology. Quantum Dot Cellular Automata QCA is a novel emerging technology in which logic states are not stored as voltage levels, but rather the position of individual electrons. Conceptually, QCA represents binary information by utilizing a bistable charge configuration rather than a current switch. A QCA cell can be viewed as a set of four dots that are positioned at the corners of a square. A quantum dot is a site in a cell in which a charge can be localized. The cell contains two extra mobile electrons that can quantum mechanically tunnel between dots, but not cells. In the ground state and in the absence of external electrostatic perturbation. The electrons are forced to the corner positions to maximize their separation due to Coulomb repulsion. The two possible charge configurations are used to represent binary 0 and 1. Note that in the case of an isolated cell, the two polarization states are energetically degenerate. However the presence of other charges (neighbour cells) breaks the degeneracy and one polarization state becomes the cell ground state. The concept was originally discovered in the 1940s by Stanislaw Ulam and John von Neumann while they were contemporaries at Los Alamos National Laboratory. While studied by some throughout the 1950s and 1960s, it was not until the 1970s and Conway's Game of Life, a two-dimensional cellular automaton, that interest in the subject expanded beyond academia. In the 1980s, Stephen Wolfram engaged in a systematic study of one dimensional cellular automata, or what he calls elementary cellular automata; His research assistant Matthew Cook showed that one of these rules is Turing complete. Wolfram published A New Kind of Science in 2002, claiming that cellular automata have applications in many fields of science. These include computer processors and cryptography. The primary classifications of cellular automata as outlined by Wolfram are numbered one to four. They are, in order, automata in which patterns generally stabilize into homogeneity, automata in which patterns evolve into mostly stable or oscillating structures, automata in which patterns evolve in a seemingly chaotic fashion, and automata in which patterns become extremely complex and may last for a long time, with stable local structures. This last class are thought to be computationally universal, or capable of simulating a Turing machine. Special types of cellular automata are those which are reversible, in which only a single configuration leads directly to a subsequent one, and totality, in which the future value of individual cells depend on the total value of a group of neighbouring cells. Cellular automata can simulate a variety of real world systems, including biological and chemical ones.

3 Dammalapati Dileep, Vallabhaneni Ramesh Babu Design of 1-Bit COMPARATOR Data path components in modern high performance superscalar processors employ a significant amount of associative addressing logic based on the use of comparators that dissipate energy on a mismatch. In order to avoid the mismatch the design of comparator using microprocessor is designed. Their performance level is high but it consists of five metal layers. Hence it dissipate large amount of power. The design of two new comparator circuits that is predominantly dissipates energy on a match, thus resulting in very significant savings in comparator power dissipation. The logic structure and interconnection in the QCA cell are designed either in coplanar cross or bridge technique. QCA technology is the inverter and the majority gate (MG).These majority gates are performs with same clock signal. M (a,b,c)=a.b+a.c+b.c A 1-bit binary comparator receives two bit a and b and it compare whether a and b are equal, or greater than each other, or less than each other. This comparator is slow and d it takes large amount of power to yield the output. To overcome this problem a tree based architecture are exhibited to achieve high speed. The inputs are given to the majority gates which proceed through the proper number of cascaded in which OR, AND gates are implemented. In the tree based architecture the delay will increase according to the n bit comparator. A 1-bit QCA comparator is constructed only with three gates (two different forms of majority gates and only one inverter). In comparison to other existing implementation this method has demonstrated interesting results. Beside, some Boolean functions are expressed as examples and it has been shown, how our reduction method by applying new proposed item, decreases gate counts and levels. We will show and discuss that using of the proposed items can be efficient in designing majority gate based circuits. Implementation Results Fig.1: 1 bit comparator in QCA The 32 bit comparator circuit design is functionally verified through simulation. The simulation is performed by creating a library of reversible logic gates such as Peres gate, MG gate, Double Peres gate in Verilog. The Verilog library of reversible gates is used to implement gate level modelling of the proposed design. Using the test bench, exhaustive simulation is done to verify the functional correctness of the proposed circuit. The simulation is carried out using Xilinx 14.2 ISE simulator. Simulation result is shown in the Figure 2 to 6. Fig.2: RTL Schematic for 32 Bit Comparator

4 An Efficient design of Binary comparators in Quantum Dot Cellular Automata Fig.3.Top Level technical schematic for 32 Bit comparator A= B= Fig.4: Assigning input values to ISE simulator Simulation Comparator output in registers Fig.5: Simulator output for 32bit comparator

5 Dammalapati Dileep, Vallabhaneni Ramesh Babu Table 1: 32-Bit comparator Device utilization Summary Total Power: 0.26mW Fig.6: Power Report Conclusion and Future Scope A new methodology useful to design binary comparators in QCA has been presented. In this thesis, a novel plan for QCA cell has been acquainted with develops a 32 bit comparator. The study has had an immediate application to the outline of rationale capacities in QCA where the rationale primitives are three-and five-info greater part door. As a contextual analysis, the proposed strategy is utilized to add to a 1-bit QCA viper that is built with just two greater part doors and one inverter. Likewise, a few samples shows that our technique has impressive impact on circuits improving as our proposed thing diminish the level tallies and the quantity of greater part and inverter. It is normal that the new plan for QCA cells and the new type of larger part entryway and the lessening technique. The system is big enough to have a lot of work in the future. By connecting n-bit QCA comparator. However, this bit-serial approach requires a complicated clocking scheme. In this thesis we demonstrate that it is possible to design a QCA one-bit comparator, with the same reduced hardware as the bitserial comparator. References [1] Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata, StefaniaPerri, Senior Member, IEEE, Pasquale Corsonello, Member, IEEE, and Giuseppe Cocorullo, Member, IEEE- March [2] L. Lu, W. Liu, M. O Neill, and E. E. Swartzlander Jr., QCA systolic Array design, IEEE Trans. Computer., vol. 62, no. 3, pp , Mar [3] S. Perri and P. Corsonello, New methodology for the design of efficientbinary circuits addition inqca, IEEE Trans.Nanotechnology., vol. 11, no. 6, pp , Nov [4] V. Pudi and K. Sridharan, New decomposition theorems on majoritylogic for low-delay adder designs in quantum dot cellular automata, IEEE Trans. Circuits Syst. II: Exp. Brief, vol. 59, no. 10, pp ,Oct

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