DESIGN OF AREA DELAY EFFICIENT BINARY ADDERS IN QUANTUM-DOT CELLULAR AUTOMATA

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1 DESIGN OF AREA DELAY EFFICIENT BINARY ADDERS IN QUANTUM-DOT CELLULAR AUTOMATA 1 Shrinidhi P D, 2 Vijay kumar K 1 M.Tech, VLSI&ES 2 Asst.prof. Department of Electronics and Communication 1,2 KVGCE Sullia, D.K 1 nidhiparla@gmail.com, 2 vijayakanichar@yahoo.com ABSTRACT In the modern era of technology to increase the chip computational capabilities,decreasing the size of the transistor more and more is required so that more number of transistors can be accommodated in a single die. However transistor has certain size limit and size of the transistor cannot be reduced below certain limits. Quantum dot cellular automata(qca) is the possible solution to overcome this physical limit, even though the design of logic modules in QCA is not forever straightforward. Quantum-dot cellular automata (QCA) is considered as an advanced and alternative technology compared to complimentary metal-oxide-semiconductor (CMOS).QCA is a emerging technology used in nano-scale design. Thus our interest is to design different adders in QCA. In this brief, we propose a new adder that achieve the better area-delay trade off compared to the design known in literature. The simulations in the present work have been carried out using QCADesigner tool. Keywords: Quantum dot cellular automata(qca), metal-oxide-semiconductor (CMOS), QCADesigner tool, nano-scale design,adder 1.INTRODUCTION Quantum-dot cellular automata (QCA) is an emerging,promising and future nanoelectronic technology that offers a revolutionary approach to computing at nano-scale level [1].In 1965, Gordon Moore predicted that the number of transistors that could be integrated into a single die would grow exponentially with time. Moore's law has governed microprocessor manufacturing processes, and consequently microprocessor performance ever since. However, recent studies indicate that during the next two decades, the laws of nature will begin to govern microprocessor design and fabrication. Current CMOS technology is on verge of reaching the bound of feature size reduction. Its high power consumption also prevents the energy-efficient realization of complex logic implements at nano-scale. Also, reducing size of transistor in CMOS circuitry does not necessarily produce corresponding gains in device density. One conventional way to enhance the performance of logic system is parallelism. As an alternative to CMOS-VLSI, researchers have proposed an approach to computing with quantum dots, the quantum cellular automata (QCA). First proposed in 1994, unlike conventional computers in which information is transferred from one place to another by means of electrical current, QCA transfers information by propagating a polarization state. QCA provides high computational power and compact density for the digital circuits at nano-scale level. Computation and information transformation in QCA is different from the conventional CMOS [2]. As there are not any current in the circuit and output capacity QCA power consumption is extremely lower than CMOS.For the new design in QCA the architecture commonly employed in traditional CMOS design are considered as first reference. In this paper we proposed different types of adders such as Ripple-carry(RCA), carry look-ahead adder(cla), Brent-kung(BKA) and Novel adder. The rest of the paper is organized as follows. In Section 2, we introduce some background on QCA technology. In Section 3 we propose a new novel adder design In Section 4 we present simulation results obtained from QCADesigner Finally, we conclude the paper in Section 5. 2.BACKGROUND Canara Engineering College Mangalore NJCIET

2 QCA cells perform computation by interacting Coulombically with neighboring cells to influence each other's polarization. In the following subsections we review some simple, yet essential, QCA logical devices: a majority gate, QCA inverter. 2.1The basic QCA device A high-level diagram of a four-dot QCA cell appears in Figure 1. Four quantum dots are positioned to form a square. Quantum dots are small semi-conductor or metal islands with diameter that is small enough to make their charging energy greater than kbt (where kb is Boltzmann's constant and T is the operating temperature). Exactly two mobile electrons are loaded in the cell and can move to different quantum dots in the QCA cell by means of electron tunneling. Tunneling paths are represented by the lines connecting the quantum dots in 1. Coulombic repulsion will cause the electrons to occupy onlythe corners of the QCA cell resulting in two specificpolarizations. This figure represents places where the electrons are as far as possible from each other without escaping the confines of the cell. Electron tunneling is assumed to be completely controllable by potential barriers that can be raised and lowered between adjacent QCA cells by means of capacitive plates. Fig.1 QCA cell polarizations and representations of binary 1 and binary 0. For an isolated cell there are two energetically minimal equivalent arrangements of the two electrons in the QCA cell, denoted cell polarization P = +1 and cell polarization P = -1. Cell polarization P = +1 represents a binary 1 while cell polarization P = -1 represents a binary 0. This concept is also illustrated graphically in Fig QCA Majority Gate Different logic gates can be formed using the QCA cells. The QCA majority gate has 3 inputs and an output. It performs a threeinput logic function.qca majority gate layout is shown in Fig. Assuming theinputs are a, b and c, the logic function of the majoritygate is M (a, b, c) = ab+bc+ac. Fig.2 QCA majority gate An AND gate or OR gate can be obtained by setting the polarization of one input to the QCA majority gate as logic 1 or logic 0,respectively[3]. Canara Engineering College Mangalore NJCIET

3 2.3 QCA Inverter An inverter is usually formed by placing the cells with only their corners touching. The electrostatic interaction is inverted, because the quantum dots corresponding to different polarizations are misaligned between the cells [4] 2.4 CLOCKING Fig.3 QCA inverter design In the QCA circuits there is no external source for powering the cells hence it requires a clock. Clock synchronize and control information flow and also provide the power to run the circuit. Clock has four different phases.the four different phases are switch, hold, release and relax.during the first clock phase, the switch phase, QCA cells are unpolarized andtheir interdot potential barriers are low. The QCA cells become polarized according to the state of their input cell when the barriers are raised in this phase. The actual computation (or switching)occurs in this phase. By the end of this clock phase, barriers are high enough to suppress any electron tunneling and cell states are fixed. During the hold phase, barriers are held high so the outputs of the subarray can be used as inputsto the next stage. In the third clock phase, the release phase, barriers are loweredand cells are allowed to relax to an unpolarized state. Finally, during the fourthclock phase, the relax phase, cells remain in an unpolarized state because cell barriers remain lowered. [5]. Two different ways of four clock phases are illustrated below in Fig 4 Fig.4 QCA clock zones and clock phases 2.5 Different QCA adders Ripple Carry Adder (RCA): The ripple carry adder (RCA) provides a slow and efficient method for adding two binarynumbers. The RCA process n-bit operands by cascading n full-adders (FAs). RCA constructed using the majority gate and inverter. They have a carry-in to carry-out path consisting of one MG, and a carry-in to sum bit path containing two MGs plus one inverter.thus by cascading n-full adder we get n-bit RCA [6].For high speed operation two types of full adders are used [7].The carryout of Jth full adder is used as the carry in the (J+1)th full adder as shown in the Fig.5. Canara Engineering College Mangalore NJCIET

4 Fig.5 Ripple carry adder using QCA Carry Look Ahead Adder: The carry lookahead adder(cla) has a regular structure.it achieves high speed. These adders avoid feedback signals that are used in regular CMOS. By the nature of QCA cells the carry lookahead adder is pipelined. In the PG block we have a generated output that indicates that a carry is generated at bit position and a propagate output that indicates that a carry entering bit position will propogate to the next bit position.thus these are used to produce all the carries in parallel at the successive blocks.dueto the pipeline diagram all sum signals are available at the same clock period. In Fig.6 we represent design of CLA. Ci=Gi+Pi.C_1 Fig.6 Carry look ahead adder using QCA Brent Kung Adders: The parallel-prefix BKA demonstrated exploits more efficient basic CLA logic structures. As its main Advantage over the previously described adders, the BKA can achieve lower computational delay. The Brent kung adder uses an associative operator called as dot operator (0).The dot operator impliesthe associative property.the associative property is given as a.(b.c)=(a.b).c By applying these conditions combining n arguments using the dot operator can be executed.thusthis property can be applied to n-bit adders [6]. The dot operator establishes the relationship betweenthe two tuples(g,p) where 0 is the fundamental carry operator.in particular for radix-2 operation the operator 0 is a function that takes two inputs (g,j,pj)and (gi,pi) and produces output (g{,p{}}) at each bit the carry is given by C=GjcPij-0+0.c_1 Where c_1 is the primary carry input if there is no primary carry input then Cj is simply C. Fig.7 shows the representation of Brent kung adder andequations used in calculating[8]. Fig.7Brent Kung Adder using QCA Canara Engineering College Mangalore NJCIET

5 3.PROPOSED METHOD Novel QCA adder Fig.8 2-bit Novel QCA adder To construct Novel QCA adder, considertwo n-bit addends A = an-1,..., a0 and B = bn-1,...,b0 and suppose for the ith bit position the propagate signal is given by Pi = ai +biand generate signal is Gi = ai bi, are computed. Ci being the carry produced at the generic (i-1)th bit position, the carry signal Ci+2 at the (i+1)the bit position can be computed using the CLA logic Fig.9 Novel n-bit adder (a) carry chain (b) sum block Conversely, conventional circuits operating in the RCA fashion, namely the RCA and the CFA, require two cascaded MGs to perform the same operation. In other words, an RCA adder designed as proposed has a worst case path almost halved with respect to the conventional RCA and CFA. Canara Engineering College Mangalore NJCIET

6 4.IMPLEMENTATION AND RESULTS The proposed addition design is implemented for several operands word lengths using the QCA Designer tool adopting the same rules and simulation settings used. Fig 10 QCA design for CLA Fig.11 Novel QCA adder Canara Engineering College Mangalore NJCIET

7 Fig.12 Simulation result 5. CONCLUSION In this paper, we have considered primitives in QCA and have presented an efficient QCA design for an Novel adder and various prefix adders.we have found that the Novel adder adder has lower delay than all other adder designs Further, the Novel adder performs best among the other adders in terms of delay. References [1] C. S. Lent, P. D. Tougaw, W. Porod and G. H. Bernstein, Quantum Cellular Automata, Nanotechnology, Vol. 4, No. 1, 1993, pp [2] I. Amlani. Digital logic gate using quantum-dot cellular automata. Science, 284:289, [3] P.D.Tougaw and C.S.Lent, Logical devices implemented using quantum cellular automata, Journal of Applied Physics, vol.75, no.3, pp , February1, [4]W. J. Townsend and J. A. Abraham, Complex Gate Im- plementations for Quantum Dot Cellular Automata, Pro- ceedings of the 4th Conference of Nanotechnology, Munich, August 2004, pp IEEE [5] Craig S. Lent and P. Douglas Tougaw. A device architecture for computing with quantum dots. Proceedings of the IEEE, 85:541, [6]. R. Zhang, K. Walus, W. Wang, and G. Jullien. Performance comparison of quantum-dot cellular automata adders. In IEEE International Symposium on Circuits and Systems, 2005, pages , 2005 [7]. H. Cho and E. Swartzlander. Pipelined carry lookahead adder design in quantum-dot cellular automata. In Conference Record of the Thirty-Ninth Asilomar Conference on Signals, Systems and Computers, 2005, pages ,2005. [8]. Brent Kung, A regular Layout for Parallel Adders, IEEE, 1982 Canara Engineering College Mangalore NJCIET