DESIGN OF PARITY GENERATOR AND PARITY CHECKER USING QUANTUM DOT AUTOMATA

Transcription

1 Volume 118 No ISSN: (on-line version) url: DESIGN OF PARITY GENERATOR AND PARITY CHECKER USING QUANTUM DOT AUTOMATA MummadiSwathi 1, UdariGnaneshwara chary 2 Asst Professor Dept. of CSE, B.V.Raju Institute of Technology, Narsapur, Medak. April 30, 2018 Abstract Lossless data transmission is very important in digital data communication. An ultra-high speed Quantum dot cellular automata (QCA) is an emerging technology which transfer the information with high speed and low power. In this paper, we are going to explain about the design of even and odd parity generator and checker circuit for 3 and 4 bits. The proposed 4 bit parity checker circuit occupies an area of um 2. QCA designer 2.0 is used for all proposed layouts. Key Words:QCA, Parity Generator, Parity Checker, Qubit. 1 Introduction In computer networks, while data transmission there is a possibility of getting errors that is data loss. The role of parity generator is, it generates parity bit while data is transferred from one device to other device. In this we have even parity and odd parity based on number of ones in the transferring data. The role of Parity checker is to check whether the received data has any errors, these errors 1

2 will identified based on parity bit. So by using parity checker one can identify the errors in the data so it is easy to rectify errors while data transmission from one device to other device. Quantum technology is one of the emerging technology which making lot of changes in high speed computing. Quantum technology is one of the emerging technologies in the field of Nano technology. It deals with the quantum dots which are represented in the form of Square Shape which is called as Qubit. 2 QUANTUM DOT COMPUTING AU- TOMATA(QCA) BACKGROUND Qubit consist of 4 quantum dots in which QCA cell is charged with two excess electrons which is allowed to tunnel between the quantum dots by a mechanism called clocking. Cross corners of the two dots are charged by the polarization. Below figure shows the QCA cell with Polarization 1 and Polarization 0. Polarization 1 represents the logic 1 and Polarization 0 represents the Logic 0. Fig 1: Basic Qubit cells 3 QCA WIRE REPRESENTATION A horizontal connection of QCA cells are makes the wire and because of the electrostatic interactions between the cells a binary values propagates from input to output. 2

3 Fig 2: QCA wire logic QCA wires are classified into two types depends on the quantum dot rotation. The wire which shown in figa is connected in 900 and connection in the fig b represents the 450 wire. Sasamal [1] proposed a five input majority voter XOR Gate with coplanar QCA technology. This design mainly consists of five inputs and rotated three input majority gate, Number of clock cycles In this proposal total 1126 cells are used to design a 32-bit parity generator.santanusantra [2] Proposed a XOR gate in two different approaches of XOR gate, One of the XOR gate takes 51 number of cells with 5clock cycles. In this design with the inputs are used outside of XOR structure. The area taken for this circuit is 16524nm. In second method, they proposed XOR structure with 30 numbers of cells and it consists of four clock cycles only and area is 9720nm 2. Ilanchezhian[3] proposed a241 cells 3 bit parity generator with area is um 2. The XOR gate which is used in the parity generator consists of 64 cells with area of m 2. They also proposed a parity checker with 197 cells and area is 293.6m 2.Kakalidutta[4] proposed a XOR gate based on two dot one electron QCA method. In this, two quantum dots are used in which one electron is free to move between the cell dots. They designed the parity generator and checker based on this proposed XOR gate. This is mainly represents reversible logic.trilokyanathsasamal[5] Proposed a 32 bit parity generator circuit using three input majority voter gate XOR logic. Which taken 40% less cells compared to previous logics.ali NewazBhava[6] proposed three input majority voter XOR gate. XOR gate consists of only 10cells and 4 parity generator taking only 24 cells and 8bit parity generator designed by using only 51 cells.in this work, we designed a 3bit, 4 bit and 8 bit parity checker circuit based on Newazbahar XOR design. 3

4 Fig 3: 2 input XOR gate Fig 4:3 input XOR gate Fig 5:3 input XNOR gate 4

5 Fig 6: 3 input XNOR gate 4 MAJORITY GATES There are so many types of Majority gates are available in QCA. Example 3 input majority gate which consist of MV(A,B,C) where MV indicates Majority Voter gate. MV(A,B,C) = AB+BC+CA; MV(A,B,0) =AB; MV(A,B,1)=A+B; 5 PARITY GENERATOR CIRCUIT Depends on number of ones in data parity bit is generated. Input for the parity generator is n-1 bit stream data and it generates additional bit which should transmit with bit stream i.e. parity bit. Parity generator is two types. 1. Even parity generator 2. Odd parity generator. 6 EVEN PARITY GENERATOR In bit stream number of 1s are checked, if the number of 1s are even then 0 is added as a parity bit if the number of 1s are odd then 1 is added as a parity bit Example consider the 3bit even parity generators Table 1: 3 bit parity generator 5

6 Fig 7: conventional 3 bit parity generator circuit Fig8 : parity generator circuit using 3 input XOR If we rearrange the circuit with 3 inputs XOR gate, this number of XOR gates are reduced to 1. QCA 3 bit parity generator 3 bit even parity generator circuit designed based on 5 input majority voter gate logic. For odd parity generator 3 input XNOR gate is used, parity generator taken 10 cells with 2 clocks. 6

7 Fig 9: QCA 3 bit even parity generator Fig10: QCA 4 bit even parity generator 7 PARITY CHECKER CIRCUIT In communication system when the data is transferred from one system to other system there is chance of getting errors, so to avoid this problem a Parity bit will be sendto the other system with data, if there is any loss of data that will be detected using this parity bit which represents even or odd number of 1s in the transferred data. Parity checker is the process of determining whether the received data has any errors or not based on the parity bit which is generated by parity generator. In this we may have odd parity or even parity based on number of 1s in data. For example consider the 8-bit data will have even parity because number of 1s are 4 that is even.this circuit consists of only 10 cells to implement 3-bit parity generator. 3-bit parity checker: Table2: 3 bit parity checker 7

8 The output of the parity checker mainly depends on number of 1s, if number of 1s are even output is 1 otherwise output zero. After rearranging above circuit Fig 11: Even Parity checker By using Newazbahar 3 inputs XOR gate numbers of cells required to design the above circuit in QCA layout is 20. ODD PARITY CHECKER: In odd parity checker, odd parity bit is X-NORed with remaining input bits A, B, C Fig

9 Fig 13: 3 bit odd parity checker Fig 14: 4 bit odd parity checker As per the logic of parity checker for 4-bit data 3 XOR gates are required. In below figure parity checker is designed by using 2 input QCA XOR gates with less number of cell count and area also small compared to the previous structures. 8 RESULTS Fig15 :3 bit even parity generator 9

10 Fig16:4 bit odd parity generator Fig 17: 3 bit even parity checker Fig18 : 4 bit odd parity checker 10

11 9 CONCLUSION Three input and Four input even and odd parity generators and parity checkers are designed based QCA logic and no of cells and area also compared. Compared to previous designs less no of cells and area obtained. References [1] Cho, H. and Swartzlander, E. E., Adder and multiplier design in quantum-dot cellular automata, IEEE Transactions on Computers, 58(6), 2009, [2] Lent C.S., Tougaw P.D., Porod W.D., and Bernstein., G.H. Quantum cellular automata, Nanotechnology, 4(1), 1993, P. S. Huang, C. S. Chiang, C. P. Chang, and T. M. Tu, Robust spatial watermarking technique for colour images via direct saturation adjustment, Vision, Image and Signal Processing, IEE Proceedings -, vol. 152, pp , [3] Seminario J.M, Derosa P.A, Cordova L.E and Bozard B.H., A molecular device operating at terahertz frequencies, IEEE Transactions on Nanotechnology, 3(1), 2004, [4] Zhang, R., Walus, K., Wang, W., and Jullien, G. A., A method of majority logic reduction for quantum cellular automata, IEEE Transactions on Nanotechnology, 3(4), 2008, [5] Hnninen, I. and Takala, J., Binary adders on quantum-dot cellular automata. Journal of Signal Processing Systems, 58(1), 2010,

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