Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates
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1 International Journal of omputer pplications ( ) Volume 66 No.9, March 23 Design of Fault Tolerant Reversible Multiplexer based Multi-oolean Function enerator using Parity Preserving ates Rakshith Saligram Shrihari Shridhar Hegde Shashidhar Kulkarni H R hagyalakshmi M K Venkatesha 2 Dept. of Electronics and ommunication MS ollege of Engineering Visvesvaraya Technological University angalore, India STRT Reversible logic is one of the emerging fields of research in the areas of low power computation, Optical information processing, Fault tolerant system, bio information, quantum computation and nanotechnology. LU is the most vital component of any processing system and need to consume as much less energy as possible in the mean while must be resistant to faults. In this paper the design of a fault tolerant function generator is brought out that can generate up to 6 different oolean Functions. This unit is the logical unit of an LU. Keywords Reversible Logic, Parity Preserving ates, Multi-oolean Function enerator, Logic Unit, Nanotechnology.. INTRODUTION Modern digital circuits offer a great deal of computation. s technology evolves and many more transistors can fit in a given area, the concern for power dissipation as heat arises. Landauer [] has shown in that for every erased bit at kt ln2 J of energy is lost, where k is oltzmann s constant, T is the circuit temperature in degrees Kelvin. lso, according to Moore s law, the number of transistor elements doubles roughly every two years and if this trend continues to hold, in the near future more and more energy will be lost due to bit erasures and cooling than doing computations. ennett has shown in [2] that this problem could be avoided if reversible logic is used. In reversible logic computations, there are no bit erasures and energy is conserved, thus no heat is dissipated. In order to be able to have reversible logic computations a new set of gates are required. Reversible gates are gates that have a one-to-one and onto relationship between inputs and outputs, that is they are bijective. LU is the heart of any processing unit and it performs both arithmetic and logical operations. In most of microcontroller applications, the logical operations are performed more number of times than the arithmetic operations. Thus the logical unit is critical and the design of this unit has to be done with utmost care taken. The fault may creep into this system due to many reasons. It thus becomes necessary to design a system that is fault tolerant. Parity preservation technique is one of the widely used methods for designing a fault tolerant system. parity preserving reversible logic gate is one where the parity of the inputs matches the parity of the outputs. Parity checking technique is an error detection mechanism used in digital logic and data communication systems. This is because most of the arithmetic functions are not parity preserving. If the parity of the input data is 2 Dept. of Electronics and ommunication RNS Institute of Technology Visvesvaraya Technological University angalore, India maintained throughout the computation, no intermediate checking would be required. sufficient requirement for parity preservation of a reversible circuit is that each gate be parity preserving. Thus, parity preserving reversible gates are needed to construct parity preserving reversible circuits. In this paper a function generator that can produce 6 oolean functions is designed. The rest of the paper is organized as under: Section 2 gives a walkthrough the reversible logic encompassing the basic definitions, the basic and the parity preserving reversible logic gates. Section 3 gives the design of the oolean function generator. Section 4 gives the simulation results and the conclusions. 2. REVERSILE LOI 2. Definitions Some of the basic Definitions [] Pertaining to Reversible Logic are Definition : Reversible Logic Function reversible logic function is a function which maps each input vector to a unique output vector. function is said reversible if, given its output, it is always possible to determine back its input, which is the case when there is a one-to-one relationship between input and output states. Definition 2: Reversible Logic ate reversible logic gate is a device which performs such a one to one mapping. If a reversible logic gate has N inputs, then to perform one to one mapping, the number of outputs should also be N. Then this device is said to be an NxN reversible logic gate. The inputs are denoted by I I 2 I 3 I N and the outputs are denoted by O O 2 O 3 O N. Definition 3: arbage These are the outputs that are not used in the synthesis of a function. These may appear to be redundant but are very essential for preserving the reversibility of a gate. It is denoted by O. Definition 4: onstant Inputs These are the inputs that have to be maintained at either a constant or at constant in order to generate a given logical expression using the reversible logic gates. It is abbreviated as I. Definition 5: Quantum ost This refers to the cost of the circuit in terms of the cost of a primitive gate. It is computed knowing the number of 2
2 International Journal of omputer pplications ( ) Volume 66 No.9, March 23 primitive reversible logic gates (* or 2*2) required to realize the circuit. It is denoted as Q. Definition 6: ate ount This refers to the number of gates that are present in the given reversible logic circuit. It is denoted by. nother parameter that can be defined in relation to the gate count is the flexibility, which can be defined as the ability of a reversible logic gate in realizing more functions. Higher the flexibility of a gate, lesser is the number of gates that are needed to implement a given function, lesser is the gate count. For example the VMF gate [8] has more flexibility compared to Feynman, Toffoli and Peres ates. Definition 7: Hardware omplexity The hardware complexity [9] is measured by counting the number of ND operations, number of EX-OR operations and number of OR operations. Let α = No. of EX-OR operations β = No. of ND operations δ = No. of NOT operations Then the total hardware complexity T is given as sum of EX- OR, ND and NOT operations. 2.2 asic Reversible logic gates Some of the fundamental reversible logic gates encountered in the literature are the Feynman ate [3], the Peres ate [4], the Toffoli ate, and the Fredkin ate [5]. The Feynman ate is the only 2x2 gate. The Fredkin and the Toffoli gates are the universal gates. Peres gate, though not universal is useful in implementing many functions. The basic reversible logic gates are as shown in the figure. Feynman ate Some of the parity preserving reversible logic gates are the Double Feynman ate [], Fredkin ate, New Fault Tolerant ate (NFT), PPP [2] and F2P [3]. The Parity preserving gates are as shown in the figure 2. D E D E Double Feynman ate NFT ate PPP F2P ( ) D ( )D ( ) E(+D)+ D( E)+ D(+E) ( ) ( D) E Fig 2: Parity Preserving Reversible Logic ates Peres ate 3. DESIN 3. Design of the Parity Preserving MUX The expression for output Y for a 2: multiplexer with inputs I and I 2 and select line S can be given as: Toffoli ate Fredkin ate + + Fig : asic Reversible Logic ates 2.3 Parity Preserving Reversible logic gates parity preserving reversible logic gate is the one in which the parity of the input matches with the parity of the output. onsider an NxN reversible logic gate with inputs I I 2 I 3 I N and outputs O O 2 O 3 O N. Then the gate will be parity preserving if and only if From the basic study of the reversible logic gates and their output expressions, it is found that the Fredkin gate can be used as a 2: MUX. This can in turn be cascaded into 4: and further into 6: MUX. Since Fredkin ate is parity preserving gate, the Multiplexer so constructed is Parity preserving. The design of 2: MUX and hence its cascade into 4: and 6: MUX is as shown in the figure 3. The designed multiplexer is used to select one of the 6 oolean functions generated using the function generator. The cost metrics of the designed multiplexers can be summarized in form of table. 2
3 International Journal of omputer pplications ( ) Volume 66 No.9, March 23 Fig 3 (a): Fredkin as a 2: MUX Fig 3(b): 4: MUX using Fredkin ates Fig 3 (e): 6: MUX using Fredkin ates Fig 3(c): 8: MUX using Fredkin ates Table : omparison of ost Metrics of different Multiplexers MUX O Q T 2: 2 5 2α+4β+2δ 4: α+2β+6δ 8: α+28β+4δ 6: α+6β+3δ 2 N : 2 N - 2 N +N- 5(2 N -) (2 N -)( 2α+4β+2δ) 3.2 Design of Parity Preserving Function enerator The reversible parity preserving function generator is a logic circuit that produces 6 different oolean functions. It accepts two inputs and and gives the outputs. One of these 6 outputs can be in turn selected by the 6: parity preserving multiplexer. The different operations that can be performed by the reversible function generator can be summarized in the form of a table 2. 22
4 International Journal of omputer pplications ( ) Volume 66 No.9, March 23 Table 2: Functions enerated by the Multi-oolean Function enerator oolean Function Name of Function Inputs to 6: MUX Transfer I Null I omplement I 2 omplement I 3 OR I 4 Identity I 5 Transfer I 6 EX-OR I 7 EX-NOR I 8 NOR I 9 inhibits I implies I inhibits I 2 implies I 3 The function generator is constructed using a cascade of parity preserving reversible logic gates. Firstly, two double Feynman ates are used for the purpose of fan-out generation. The three s and three s are fed to PPP, F2P and NFT gates. Some of the outputs of this stage are directly drawn out and given to the multiplexer, while few other outputs pass through a second stage of double Feynman ates where they are passed to the final output stage both in complemented form and true form. These are also selected by the multiplexer. This function generator uses a total of ten gates of which seven are double Feynman ates, one is PPP, one is F2P and other is NFT. The reversible logic structure described above is as shown in figure RESULTS ND ONLUSIONS The Fault Tolerant Reversible Multiplexer ased Multi- oolean Function enerator is tested for its functional correctness using digital adence tool. The simulation results are as shown in figure 6. This function generator can produce effectively 6 different logical functions. Most of the other function generators in the literature aim at producing only the main functions such as ND, OR, EX-OR and EX-NOR and use these functions to produce the remaining functions. The distinguishing feature of this design is that all the functions are generated within the single unit, and the designer is allowed to choose one of the functions using a multiplexer by varying the control bits, ND I 4 NND I 5 F2 PPP F2 F2 F = F = F 2 = F 3 = F 4 =+ F 5 = F 6 = F2P F 7 = F 8 =ʘ F 9 =(+) F2 F = F = + F2 NFT F2 F 2 = F 3 =+ F2 F 4 = F 5 =() Fig 4: Reversible Function enerator 23
5 International Journal of omputer pplications ( ) Volume 66 No.9, March 23 Fig 5: omplete lock diagram of Multi oolean-function enerator S S S 2 S 3. This function generator can be efficiently act as a Logic Unit of a fault tolerant reversible rithmetic Logic unit. This is design is the first of its kind in the literature to the best of the knowledge of the authors. The metrics of the complete design are: ate count is 35, garbage outputs: 26, onstant inputs: 2. s a future work we would like to implement the design using quantum dot cellular automata. Figure 6: Simulation Results of Function enerator 5. KNOWLEDMENTS The authors wish to thank the EE Department of MS ollege of Engineering, angalore, for supporting this work. 6. REFERENES [] R. Landauer, Irreversibility and Heat eneration in the omputational Process, IM Journal of Research and Development, 5, pp.83-9, 96. [2].H. ennett, Logical reversibility of omputation, IM J. Research and Development, pp , November 973. [3] R. Feynman, Quantum Mechanical omputers, Optics News, Vol., pp. 2, 985. [4]. Peres, Reversible logic and quantum computers, Phys. Rev. 32 (985) [5] E. Fredkin and T. Toffoli, onservative Logic, Int l J. Theoretical Physics Vol 2, pp , 982. [6] H.R.hagyalakshmi, M.K.Venkatesha, n Improved Design of a Multiplier Using Reversible Logic ates, International Journal of Engineering Science and Technology Vol. 2(8), 2, [7] H.R.hagyalakshmi, M.K.Venkatesha, Optimized Reversible D adder using new Reversible Logic ates, Journal of omputing, Vol 2, Issue 2, February 2 [8] H.R.hagyalakshmi, M.K.Venkatesha, Design of Multifunctional VMF Reversible logic gate and its applications Intl. Journal of omputer pplications, Vol 32, No. 3 Oct-2. [9] Md. Saiful Islam et.al Synthesis of fault tolerant Reversible logic IEEE 29. [] Rakshith Saligram and Rakshith T R Novel ode onverter employing Reversible Logic Intl. Journal of omputer pplications, Vol 52, No. 8, ug 22. []. Parhami, Fault tolerant reversible circuits, simolar onf. Signal systems and computers, October 26 [2] Krishna Murthy, ayatri, Manoj Kumar Design of Efficient dder ircuits Using Proposed Parity Preserving ate (PPP) International Journal of VLSI design & ommunication Systems (VLSIS) Vol.3, No.3, June 22. [3] Xuemei Qi and Et. l, Design of fast fault tolerant reversible signed multiplier, International Journal of the Physical Sciences Vol. 7(7), pp , 23 pril,
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