A new design and simulation of reversible gates in quantum-dot cellular automata technology

Transcription

1 A new design and simulation of reversible gates in quantum-dot cellular automata technology Moein Sarvaghad-Moghaddam, Ali A. Orouji,* Department of Electrical and Computer Engineering, Semnan University, Semnan, Iran. * Abstract Power dissipation is the main limitation of all the nano electronics design techniques including Quantumdot Cellular Automata (QCA). The reversible computing is considered as the reliable solution to lower the power dissipation. In this paper, the contribution is divided into three parts. In the first part, a multi-objective synthesis method is presented for reversible functions (with the objective priority of gate counts (majority gates), gate levels, the number of NOT gates, and control inputs which are the input cells with fixed polarization used for programming 2-input OR and AND gates). Based on the proposed method, a new synthesis of many of well-known reversible gates is proposed. In the second part, a new method for converting irreversible functions to the reversible one in QCA technology is presented. This method has advantages such as: having of a minimum number of garbage outputs, converting of irreversible functions to reversible one directly and as optimal (So, in this method, a sub-optimal method of using of conventional reversible blocks such as Toffoli and Fredkin are not used), and so on. For showing the efficiency of the proposed method, it is applied to the 3 standard combinational functions. In the third part, new designs of QCA layouts are presented for gates synthesized in the previous section. Results show that our proposed method outperforms the best available methods in terms of area, complexity (cell amount), delay (clocking zones), and also in logic level in terms of levels, Control inputs, number of majority and NOT gates.. Introduction Nano technology has been the focus of an extensive research to supersede the projected limitations of CMOS at the end of the roadmap []. One of the most pressing hurdles in the development of innovative computation paradigms and systems is energy dissipation [2]. A possible solution is reversible computing. Reversible logic was first related to energy when Landauer states that information loss due to function irreversibility leads to energy dissipation [3]. This principle is further supported by Bennett that zero energy dissipation can be achieved only when the circuit contains reversible gates [4]. Energy dissipation could be caused by information dissipation [5]. This has been quantified as KTln2 joules of energy for every bit of information that is lost, where K is the Boltzmann s constant and T is the absolute temperature of the environment. Consequently, without losing any bit of information, no energy dissipation occurs [4]. At room temperature (T = 3 K), this value is equivalent to ~2.9 2 Joules which is very small but it is important for nano-scale curcuits that must have be very low power consumption. Continuing advances in semiconductor technology have led to the reduction of feature sizes in Complementary Metal-Oxide Semiconductor (CMOS) design. More scaling of feature sizes is not possible due to physical limits such as quantum effects and non-deterministic behavior of small currents. One of the alternatives for CMOS technology is Quantum-dot Cellular Automata (QCA) [6-] in which the configuration of an electron pair within a quantum-dot cell specifies the logical states. QCA was first proposed by Lent (993) [, 2]. The fundamental unit of QCA is a QCA cell which is composed of four dots located at the corners of a square. This technology acts on the basis of Coulombic interactions of electrons trapped in quantum dots. In QCA Logic, clock is responsible for synchronization and control of information flow and also it provides power to run the circuit [6, 3]. In QCA, the three-input majority and NOT gates are the fundamental primitives. C. S. Lent et al in 25 proposed circuit design based on QCA in reversible logic [4]; then several authors proposed several reversible gates in QCA [5-8]. In [5], QCA has been investigated for testable implementations of reversible logic. Also, two new reversible gates (referred to as QCA and QCA2) have been proposed for QCA

2 implementation. In [8], a novel approach to synthesize a reversible universal QCA logic gate (RUG) structure has been proposed with the target to reduce the garbage outputs as well as the logic gates of a design. Also, RUG gate had been used for the realization of QCA logic circuits. In [9] a QCA layout design for proposed Toffoli gate has been presented. Sarker and et al. in [2] have proposed a novel design of a QCA Peres Gate (PG) and its simulation. In [2], an efficient design of the Fredkin gate has been proposed and compared with the previous designs in the number of cells, covered area and latency time. In [22], designing of a one-bit full adder has been investigated using a QCA implementation of Toffoli and Fredkin gates. Then, a full-adder design with reversible QCA gates has been proposed regarding the overhead and power savings. The output function of QCA is expressed as: Y = x x 2 + x 2 x 3 + x x 3, Y 2 = x x 2 + x x 3 + x 2 x 3, Y 3 = x x 2 + x x 3 + x 2 x 3. In [23], a multi-objective synthesis methodology (with the objective priority of gate counts, gate levels and the number of NOT gates) has been presented for finding the minimal number of possible majority gates in the synthesis of Boolean functions using the proposed Majority Specification Matrix (MSM) concept. Moreover, based on MSM, a synthesis flow has been proposed for the synthesis of multioutput Boolean functions. In this paper, the main contribution is divided to three part. In the first part, by extending synthesis method proposed in [23] a multi-objective synthesis method is proposed for reversible functions (with the objective priority of gate counts, gate levels, the number of NOT gates and control inputs which are the input cells with fixed polarization used for programming 2-input OR and AND gates). Reduction of Control inputs is a new objective that is used in this paper for improving the reduction of power consumption in reversible functions. Based on the proposed method, a new synthesis for many of popular reversible gates such as Toffoli, Fredkin and so on are proposed. In the second part, a new method for converting irreversible functions to the reversible ones in QCA technology is presented. This method has advantages such as: converting of irreversible functions to reversible one directly and as optimal. (So, in this method, sub-optimal method of using of conventional reversible blocks such as Toffoli and Fredkin are not used), having of minimum number of garbage outputs, and garbage outputs do not create any additional gates (Majority and NOT gates). For showing the efficiency of the proposed method, it is applied to the 3 standard combinational functions proposed in [24] and a reversible function is created with the lowest the number of majority gate and garbage outputs. In the third part, new designs of QCA layouts are presented for gates synthesized in the previous section. Results show that our proposed method outperforms the best available methods in terms of area, complexity (cell amount), delay (clocking zones), and also in logic level in terms of gate levels, control inputs, number of majority and NOT gates. The rest of the paper is organized as follows. In Section 2, some related background materials are presented. Section 3 introduces the proposed method in detail. Section 4 presents the results and simulations, and finally, Section 5 concludes the paper. 2. Background material In this section, basic concepts in QCA technology such as Quantum-dot cellular automata and QCA devices are explained. 2.. Quantum-dot cellular automata A standard QCA cell is contained of four quantum-dots and two excess electrons located at the corners of a square as shown in Fig..a). They can occupy diagonal antipodal sites through tunneling junctions with Coulombic interaction between the electronic charges. Due to the existence of large potential barriers, it is supposed that tunneling out of the cell is not possible. As shown in Fig..b), a single QCA cell can accept two completely polarized states called cell polarization P = + (binary state) and P = (binary state).

3 Quantum Dot P=- Binary P=+ Binary Electron Localized electron a) b) Fig. : a) Illustration of a QCA cell with four quantum dots. b) QCA cell with two different polarizations. There are four manners for the QCA implementation reported so far include of Semiconductor QCA [25, 26], Magnetic QCA [27-29], Molecular QCA [3, 3], and Metal Dot QCA [32-34]. Orlov et al [35] first have introduced fabrication of the metal dot QCA cell as shown in Fig. 2.a). It consists of four metal connected by Al AlO x Al tunnel junctions. Electron beam lithography method and Shadow evaporation techniques at 5mK temperature are used for the fabrication of this cell. For generating superconductivity of the metal, a magnetic field of T is required. Electron transfer between dots creates the polarization change. Gate electrodes force to tunnel an electron to switch from one dot to the other. In the molecular manner [36], three allyl groups are used as connected in a V like structure by alkyl bridges. Fig. 2.b) show structure of molecular QCA cell in states, and NULL. In semiconductor manner [8], QCA cell can be implemented in Silicon material like GaAs/AlGaAs and four quantum dots can be fabricated with a high mobility two dimensional electron gas below the surface as shown in Fig. 2.c). In magnetic manner [37, 38], a single nanomagnet termed as magnetic island are used which have single magnetization state viz. up ( ) (binary state) or down ( ) (binary state) as shown in Fig. 2.d). Magnetic islands are fabricated from 3-nm thin film of permalloy using EBL and standard lift off technique. In this manner, QCA cells are formed by nano-sized ferromagnetic materials. a) b) c) d) Fig. 2: Illustration of QCA implementation in four different manners. a) Schematic of metal-dot QCA. b) Charge configuration of the molecular QCA, In this case positive charge (hole, shown by filled circle) transferred between different dots, creates three states ( NULL, Binary and Binary respectively). c) Schematic model of semiconductor QCA. d) Binary states and in a Single-domain nanomagnetic QCA cell QCA Logic devices QCA wire, QCA inverter, and QCA majority gate are the fundamental QCA logic devices. A line of 9 QCA cells forms a QCA wire. The wire is driven at the input cell by a cell with a fixed/held polarization [39]. The signal propagates along the wire from left to right when excited from the left most cell. A QCA wire can also be built with cells rotated by 45. This kind of wire propagates the input signal in odd cells and inversion of the input signal in even

4 cells [4, 4]. A QCA majority gate can present a three-input logic function as given in (). Where A, B, and C are the three inputs. M(A, B, C) = AB + BC + CA. () By forcing one of the three inputs of the majority gate to a constant logic or a the majority gate can be used to perform AND/OR operations as shown in the following equations: M(A, B, ) = AB, M(A, B, ) = A + B. (2) Fig. 3 shows a QCA wire in 9 and 45, inverter gate, and majority gate, respectively. a) b) c) d) Fig. 3: Representation of a) 9 QCA wire b) 45 QCA wire c) inverter gate d) QCA majority gate In QCA, there are two crossover options. They are coplanar crossings and multilayer crossovers. In the first way, one quantum wire with a 45-degree turn passes over a regular quantum wire without any interference. This approach is shown in Fig. 4.a). In the other approach, multi-layered structures are used for the passage of the quantum wires over each other. This structure is shown in Fig. 4.b).

5 a) b) Fig. 4: a) coplanar crossing wire b) multilayer crossing wire 2.3. QCA clocking In QCA, the information erasure and storage in the cell are controlled by the clock. For synchronize and information flow control in QCA circuit, Clocking is required. Two strategies have been considered for clocking QCA [42]: ) Landauer clocking: has a logically irreversible erase operation 2) Bennett clocking: has a logically reversible copythen-erase operation [2]. It has been shown that erasure without copying requires an amount of dissipated energy in the order of the signal energy. This scheme could offer a practical realization of reversible computing using QCA. Generally, four multi-phase clocking signals of phase lagging of π are applied as shown in Fig. 5.a). This type of 2 clocking system is called Landauer type [43]. During a complete cycle, each zone goes through the four phases. This zones must follow a particular order viz. C C C 2 C 3. four phases are called Switch, Hold, Release, and Relax [6]. The waveform of Bennett clocking is shown in Fig. 5.b). The principle of this clocking is to first compute the results by latching the cell array from input to output and then don t compute by the latching array to relax to an unpolarized state from output to input. a) b) Fig. 5: a) Laundauer clocking waveform. b) Bennett clocking waveform. S: switch phase, H: hold phase, Re: release phase, Rx: relax phase Simulation tool In this paper, QCA designer software [44] which is a well-known simulation tool for complex QCA circuits is used to simulate proposed circuit layouts and functionality checking and verify reversible functions in a bistable approximation [8, 35, 45, 46].

6 The bistable simulation engine supposes that each cell is a simple two-state system. For cell i the polarization state of the cell can be shown by Eq. (3) [44]. P i = E k i,j 2γ j P j +( E k i,j 2γ j P j) k Where P j the polarization state of the neighboring cells and E i,j is the kink energy between cell i and j. γ is the tunneling energy of electrons within the cell. The summation is over all cells within an effective radius of cell i, and can be set prior to the simulation as shown in Fig. 6. (3) Fig. 6: Effective Radius k The Kink energy E i,j represents the energy cost of cells i and j having opposite polarization. It is calculated simply from the electrostatic interaction between all the charges (mobile/immobile). That is, for each dot in cell i we calculate the electrostatic interaction between this dot and each dot in cell j as shown in Eq. (4). E k i,j = q i q j 4πε ε r r i r j Where ε is the permittivity of free space and ε r is the relative permittivity of the material system. (4) 2.5. Reversible logic In addition static and dynamic power consumption, which are two well-known sources of power dissipation in a logic circuit, information loss is another source of energy loss in a logic circuit which was introduced by Landauer (In 96) [3]. According to Landauer s principle, the loss of one bit of information, will dissipate ktln (2) joules of energy where K is the Boltzmann s constant and T is the absolute temperature of the environment. This amount is According to the second law of thermodynamic. At room temperature (T = 3 K), this value is equivalent to ~2.9 2 Joules which is very small but it is important for nano-scale curcuits that must have be very low power consumption. This principle is further supported by Bennett that zero energy dissipation can be achieved only when the circuit contains reversible gates [4]. Reversible computing considers the relation between information dissipation and energy dissipation at the logical level. Reversible computation is achieved at a logical level by establishing a one-to-one mapping between the input and output vectors in the circuit [4]. The one-to-one mapping is named bijective property. In addition, fan-out is not possible in reversible systems in quantum technology. However, it should be pointed out that in QCA technology, the Majority Voting (MV) function is logically irreversible because the information in the minority input is lost during the computation. It has been shown in the literature that in QCA, another clocking arrangement that is referred as Bennett clocking can be used for reversible computing. By using this scheme can offer

7 a practical realization of reversible computing using QCA. It has been shown by direct calculation that with Bennett clocking, energy dissipation per switching event is much less than ktln2 for QCA circuits with devices such as MV and fan-out and don t exist any physical limitation [2, 42]. So, for creating reversible gates in QCA technology, fanout is not a necessary feature. Bennet clocking scheme has been introduced in QCA Clocking section Basic reversible gates A reversible gate realizes a reversible function. A logic function is reversible if and only if there is a one-to-one mapping between its input and output vectors [47]. Some of the essential reversible gates such as Fredkin gate [48], Toffoli gate [47], RUG gate [49] and Peres gate [5] are shown in Fig. 7. As shown in Fig. 7.a) Fredkin gate has a control line so that if control line A is one then, two inputs B and C are swapped in output. Fig. 7.b) show a Toffoli gate. This gate has two control lines A and B, so that if each two control lines be one then input C is inverse in output. RUG gare is shown in Fig. 7.c). This gate create a majority gate in output A and in outputs B and C act as equations AB + A C and BC + B C, respectively. Peres gate is shown in Fig. 7.d). This gate act as a Toffoli gate in output C and act as exclusive OR inputs A and B in output B. Toffoli and Fredkin gates are both universal, i.e., each logical reversible circuit can be implemented using one of these gates. a) b) c) d) Fig. 7: Reversible gates: a) Fredkin gate b) Toffoli gate c) RUG gate d) Peres gate Evaluation metrics of reversible circuits Evaluation of the designed circuits is an important issue in the synthesis of reversible logic circuits. to evaluate and compare different reversible designs the following metrics are used [5]: Number of gates can be used as a metric in circuits where gates have similar size and type. In QCA technology, Majority and NOT gates are fundamental gates. So, in this paper, number of Majority and NOT gates are used as an evaluation metric. Number of levels in the circuit which are required to realize the given logic functions. Delay that can be stated as the number of clocking zones in QCA technology. Number of Constant inputs and Garbage outputs that the unused outputs are used to maintain the reversibility of the circuits and are known as the garbage outputs. The constant inputs in the reversible circuits are called ancilla. Control inputs that is a new important feature that we add in this paper for evaluation metrics of reversible circuits in QCA technology. This feature is referred to the number of AND/OR gates used in the circuit. For creating this gates using majority gate in QCA technology, constant inputs is necessary that this redundancy constant inputs generate extra heat. 3. Proposed method In this section, the proposed method is explained. First, a multi-objective synthesis method is presented for reversible functions. Then, based on this method, a new synthesis for many of common reversible functions is presented. Then for these functions, a new design of QCA layout is proposed. After that, a new method for converting reversible functions to reversible one is proposed. 3.. Multi-objective synthesis method In this section, by extending the synthesis flow proposed in [23], with adding an important objective to previous synthesis flow, a multi-objective synthesis method for reversible functions is presented. In this paper, in addition to objective priorities proposed in [23] which include the gate counts (the number of majority gates), gate levels and the number of NOT gates, another objective namely Control inputs is used. This objective is considered for first time in this paper. One of the important objectives in creating reversible functions in the QCA technology is reducing of the

8 number of AND/OR gates that need to redundancy constant inputs. As in QCA technology, AND/OR gates are generated using Majority gate and it needs to redundancy constant inputs and because these gates are irreversible, so, these redundancy constant inputs generate extra heat. Because of that, Landauer et al [3] have shown that whenever there is a loss of information during some computation, energy is dissipated in the form of heat. So, for creating reversibility in QCA technology, the number of AND/OR gates must be reduced. Hence, in addition to objectives proposed in [23], numbers of redundancy constant input which is called control inputs is considered as latest objective. The other steps and explanations in synthesis flow are same as proposed in [23]. Fig. 8 show this synthesis flow as rewritten for reversible functions. in this figure, MSM, denote Majority Specification Matrix proposed in [23]. Input: a given specification of reversible function Output: a synthesized reversible gate using of majority gate. Create the MSM according to the number of inputs of function 2. For each of fi (i = : m m: the number of outputs of function) 3. { For each of MSMs created 4. { Find the most similar column to specification of the main function in MSM 5. Find the most similar column according to features of a combination of columns in MSM. 6. Find the most similar specification between the main function and columns of inputs. 7. Repeat Lines 4 and 5 for complementary function (fi), again. 8. Repeat Lines 4 and 5 of the algorithm for all methods explained in [23] and save the results. 9. Apply the method of conventional K-map to the main function and save the result. } }.. Use majority expression created in each of fi for synthesis other fj (j i). Select results to the most common expressions between outputs. 2. For reducing the number of NOT gates, use the following feature Maj(a, b, c ) = Maj(a, b, c) Fig. 8: Synthesis flow for synthesis of reversible functions One of the mostly used reversible logic gates is Fredkin gate or controlled-swap gate. It is 3 3 reversible gate. For instance, in the following applying the synthesis flow for the synthesis of Fredkin gate is explained. Specification function of Fredkin gate are shown in Table. Table : Specification function Fredkin gate a b c P Q R a b c P Q R For the synthesis of the reversible gate by applying the synthesis flow, first, a column of outputs that is equal to corresponding input columns is separated (output column P in Table ); then other outputs according to proposed synthesis flow are synthesized (Q and R). Table 2 and Table 3 show the synthesis of the outputs of Q and R, respectively. First, the most similar column is selected (c), by using a post-processing method explained in [23], specifications F 2 and F 3 are obtained as shown in Table 2 (Columns 4 and 5). Table 2: Synthesis of output Q from Fredkin gate

9 a b c Q F = c F 2 F 3 X = X = X = X = X = X = X = X = X = X = Boolean expressions for F2 and F3 are: F 2 = b + a = Maj(b, a, ), (5) F 3 = a b = Maj(a, b, ). The total expression for the specification function Q is: Q = Maj(c, Maj(b, a, ), Maj(a, b, )). (6) Table 3: Synthesis of output R of Fredkin gate a b c R F = c F 2 F 3 X = X = X = X = X = X = X = X = X = X = As shown in Table 3, first, the most similar column is selected (column of input c), then, Boolean functions of F2 and F3 are obtained as the expressions shown in (7): F 2 = a + b = Maj(a, b, ) (7) F 3 = ab = Maj(a, b, ) The final Boolean expression for R is: R = Maj(c, Maj(a, b, ), Maj(a, b, )) (8)

10 The number of majority and NOT gates are 6 and ; thus, the number of total gates needed for the creation of Fredkin gate is 7. Based on above method, a new synthesis of other popular reversible functions (except Fredkin that explained in above) such as Toffoli gate, RUG, Peres and reversible full-adder are presented in Table 6. In this table, underlines show fanouts. Also, for synthesizing reversible full-adder, specification function introduced in [22] are used Converting irreversible functions to reversible functions In this sub-section, a new method for converting irreversible functions to reversible ones is proposed for the QCA technology. To this end, first, common states in outputs are marked, then, input columns are compared with outputs and input column that can remove the most common states in outputs is selected and added as a new column in output. This work is repeated until common states in outputs the deleted fully and the one to one mapping between the outputs and inputs is created. By using this method, directly each type of reversible functions with the minimum complexity, area, garbage outputs, control inputs and delay can be created while the other methods such as [52-54] have used popular reversible blocks such as Toffoli and Fredkin gates or building of reversible blocks (intermediate reversible blocks) for designing other reversible functions which these methods are not optimal. Finally, the obtained reversible function is synthesized using the proposed method in Section 3.. Proposition: by using the above method a reversible function with the lowest number of majority gate and garbage outputs is created. Proof: Suppose the number of function inputs is n, thus there are 2 n states in the truth table where in each of columns, half ( 2n ) of states are ones and other half 2 (2n ) are zeros. Then, the following two cases may be occurred for the function 2 outputs.. If the number of ones in output is not equal to 2n, then for creating reversibility in the output, at least n inputs 2 should be added to them, as a reversible function needs 2 n distinct states in the output. On the other hand, the number of garbage outputs is equal to the number of inputs and thus no extra majority gate is created. 2. If the number of ones in the output is equal to 2n, then reversibility can be obtained by n garbages such 2 that these extra outputs are not equal to input orders. Thus, these outputs lead to extra majority gates. In addition, extra majority gates can be deleted if garbage outputs are equal to function outputs; but this leads to common states created in the output without reversibility. But reversibility can be obtained when n inputs are added to the output. Then, a reversible function is generated with the lowest number of majority gates and garbage outputs The 3 standard combinational functions For verification, the proposed method is applied to the 3 standard combinational functions introduced in [24] which are initially utilized for comparison purposes. These functions represent all 256 three-variable Boolean functions. First, the 3 standard combinational functions must be converted to reversible functions. Finally, the obtained reversible function is synthesized using the proposed method in Section 3.. For comparison, the number of gates and the number of clocking zones of the 3 standard functions implemented using each of the four reversible gates by [55] are reported in Table 4. It points to the fact that the realization of a logic circuit using the proposed method can result in better cost-effective designs than those of with other conventional reversible gates in terms of the numbers of majority, NOT gates and clocking zone. The obtained circuits of 3 standard functions shown in Table 4 are illustrated the appendix.

11 Table 4: Reversible implementation of 3 standard functions Fredkin+Inverter Toffoli+Inverter QCA QCA 2 Proposed Method Functions Clk Clk Clk Clk Clk Majority NOT Majority NOT Majority NOT Majority NOT Majority NOT zone zone zone zone zone F=AB'C F2=AB F3=A'BC+A'B'C' F4=A'BC+AB'C' F5=A'B+BC' F6=AB'+A'BC F7=A'BC+ABC'+A'B'C' F8=A F9=AB+AC+BC F=A'B+B'C F=A'B+BC+AB'C' F2=AB+A'B' F3=ABC'+A'B'C'+AB'C+A'BC

12 3.4. New design of QCA layout of reversible functions In this sub-section, new designs of QCA cell layouts for popular reversible logic gates are shown in Fig. 9. These layouts are related to reversible gates synthesized in above sections including Toffoli, Fredkin, reversible full-adder, RUG, and Peres, respectively. a) b) c) d) e) Fig. 9: QCA cell layouts of reversible logic gates. a) Toffoli gate b) Fredkin gate c) reversible full adder d) RUG gate e) Peres gate. 4. Results In this section, first a comparison between the proposed synthesis method and the best obtained results are done. Then, the simulation results of the obtained circuits are presented. 4.. Comparison results As shown in Table 6, the proposed method is compared with the best existing obtained results for popular reversible gates in logical level. In this table, in addition to the number of majority and NOT gates and levels, the number of Constant inputs is considered as an objective. Synthesized circuits are shown in the final column of this table. As shown in this table, the proposed approach results in fewer majority gates, NOT gates, Constant inputs, and fewer logic levels as compared to existing methods [8-22]. Also, reduction of the number of Control inputs as an objective in algorithm has led to reduction of the numbers of AND/OR gates and it results in the reduction of power consumption. In this table, for synthesizing reversible full-adder, specification function introduced in [22] is used. In addition, a detailed comparison between the proposed implementation and the best presented implementations is performed in Table 7 from different aspects which include area, cell amount and the number of clocking zones. Clearly, our designs outperform the proposed designs in [8 22] with respect to the area, cell amount and the number of clocking zones in the design of QCA layouts.

13 4.2. Simulation results As stated in Section 2.4, in this paper, QCA designer is used for simulation of the proposed designs. Simulator version is 2..3 and parameters used in this software are shown in Table 5. Also, simulation results related to new design of QCA layouts of reversible functions include of Toffoli, Fredkin, RUG, Peres and reversible full-adder (shown in Fig. 9) are shown in Fig.. Table 5: Settings of QCA designer Parameter type Value Parameter type Value Cell size 8 nm clock high 9.8e 22 J Number of samples 28 clock low 3.8e 23 J Convergence tolerance. clock amplitude factor 2. The radius of effect 65 nm layer separation.5 nm Relative permittivity 2.9 maximum iterations per sample Table 6: Comparisons with popular reversible functions Reversible gates Method Constant inputs Number of NOT gates Number of majority gates Level Synthesized circuit Toffoli Fredkin RUG Peres [9] Proposed method [2] Proposed method [8] Proposed method [2] Proposed method P=a, Q=b, R=Maj(Maj(a,b,c')',Maj(a,c,),Maj(b,c,)) P=a, Q=Maj(c,Maj(b,a,),Maj(a',b,)), R=Maj(c,Maj(a,b,),Maj(a,b,)) f=m(a,b,c), f2=m(c',m(a',b,),m(a,b,)), f3=m(c,m(b,c',),m(b,c,)') P=a, Q=M(b,M(a,b,),M(a,b,)), R=M(M(M(a,b,),c',),M(M(a,b,)',c,),c) Reversible fulladder [22] Sum=M(M(a,b,cin)',a,M(a',b,cin)), Cout=M(a,b,cin), Proposed method Gar=M(a',b,cin), Gar2=Cout, Gar3=M(a,b,cin')

14 a) Toffoli gate b) Fredkin gate c) RUG gate d) Peres gate e) Reversible full-adder Fig. : Simulation results of reversible gates in Fig. 6

15 Table 7: Performance comparison of QCA implemented reversible gates Reversible Gates Method Cell amount Area (μm 2 ) Clocking zones Toffoli [9] Proposed Method Fredkin [2] Proposed Method RUG [8] ~ Proposed Method Peres [2] Proposed Method Reversible full-adder [22] Proposed Method Conclusion In this paper, the main contribution was divided to three part. In the first part, by extending synthesis method proposed in [23] a multi-objective synthesis method was proposed for reversible functions (with the objective priority of gate counts (the number of majority gates), gate levels, the number of NOT gates and control inputs which were the input cells with fixed polarization used for programming 2-input OR and AND gates). Reduction of Control inputs was a new objective that was used in this paper for improving the reduction of power consumption in reversible functions. Based on the proposed method, a new synthesis of many of well-known reversible gates such as Toffoli, Fredkin and so on was proposed. In the second part, a new method for converting irreversible functions to reversible ones in QCA technology was presented. This method has advantages such as: converting of irreversible functions to reversible one directly and as optimal. (So, in this method, sub-optimal method of using of conventional reversible blocks such as Toffoli and Fredkin were not used), having of minimum number of garbage outputs, and garbage outputs did not create any additional gates (Majority and NOT gates). For showing efficiency of the proposed method, it is applied to the 3 standard combinational functions proposed in [24] and a reversible function was created with the lowest the number of majority gate and garbage outputs. In the Third part, new designs of QCA layouts were presented for gates synthesized in the previous section. Results showed that our proposed method outperforms the best available methods in terms of area, complexity (cell amount), delay (clocking zones), and also in logic level in terms of levels, control inputs, number of majority and NOT gates. Appendix In this section, the obtained circuits of 3 standard functions shown in Table 4 are illustrated in Table A. Table A: the obtained circuits of 3 standard functions shown in Table 4 Functions Synthesized circuit F=AB'C F2=AB F3=A'BC+A'B'C' F4=A'BC+AB'C' F=Maj(Maj(A,B,),C,), Y2=B, Y3=C, Y4=A, F2=Maj(A,B,), Y2=B, Y3=C, Y4=A F3=Maj(Maj(A',B,C'),Maj(A',B',C),), Y2=B, Y3=C, Y4=A F4=Maj(Maj(Maj(A',B,),C,),Maj(Maj(A,B',),C',),), Y2=B, Y3=C, Y4=A

16 F5=A'B+BC' F5=Maj(Maj(A,C,)',B,), Y2=B, Y3=C, Y4=A F6=AB'+A'BC F6=Maj(Maj(A,B,C),Maj(A,B',),Maj(A',B',)), Y2=B, Y3=C, Y4=A F7=A'BC+ABC'+A'B'C' F8=A F9=AB+AC+BC F=A'B+B'C F=A'B+BC+AB'C' F2=AB+A'B' F3=ABC'+A'B'C'+AB'C+A'BC F7=Maj(Maj(A',B,C'),Maj(A',B',C),Maj(A,C',)),Y2=B, Y3=C, Y4=A F8=A F9=Maj(A,B,C),Y2=B, Y3=C, Y4=A F=Maj(C,Maj(A',B',),Maj(B,C',)),Y2=B, Y3=C, Y4=A F=Maj(Maj(A,B,C'),Maj(B',C',),Maj(A',B,C)),Y2=B, Y3=C, Y4=A F2=Maj(B,Maj(B',A,),Maj(A',B',)),Y2=B, Y3=C, Y4=A F3=Maj(Maj(A,B',C'),B,Maj(A',B',C)),Y2=B, Y3=C, Y4=A References [] R. Compano, L. Molenkamp, and D. Paul, "Technology roadmap for nanoelectronics. European Commission IST Programme, Future and Emerging Technologies," ed, 23. [2] C. S. Lent, M. Liu, and Y. Lu, "Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling," Nanotechnology, vol. 7, p. 424, 26. [3] R. Landauer, "Irreversibility and heat generation in the computing process," IBM journal of research and development, vol. 5, pp. 83-9, 96. [4] C. Bennett, "Logical reversibility of computation," Maxwell s Demon. Entropy, Information, Computing, pp , 973. [5] X. Ma, J. Huang, C. Metra, and F. Lombardi, "Testing reversible D arrays for molecular QCA," in 26 2st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 26, pp [6] K. Hennessy and C. S. Lent, "Clocking of molecular quantum-dot cellular automata," Journal of Vacuum Science & Technology B, vol. 9, pp , 2. [7] C. S. Lent, B. Isaksen, and M. Lieberman, "Molecular quantum-dot cellular automata," Journal of the American Chemical Society, vol. 25, pp , 23. [8] C. S. Lent and P. D. Tougaw, "A device architecture for computing with quantum dots," Proceedings of the IEEE, vol. 85, pp , 997. [9] P. D. Tougaw and C. S. Lent, "Logical devices implemented using quantum cellular automata," Journal of Applied physics, vol. 75, pp , 994. [] International Technology Roadmap for Semiconductors (ITRS) 23. Available: [] C. S. Lent, P. D. Tougaw, and W. Porod, "Bistable saturation in coupled quantum dots for quantum cellular automata," Applied Physics Letters, vol. 62, pp , 993. [2] P. D. Tougaw, C. S. Lent, and W. Porod, "Bistable saturation in coupled quantum dot cells," Journal of Applied Physics, vol. 74, pp , 993. [3] I. Amlani, A. O. Orlov, R. K. Kummamuru, G. H. Bernstein, C. S. Lent, and G. L. Snider, "Experimental demonstration of a leadless quantum-dot cellular automata cell," Applied Physics Letters, vol. 77, pp , 2. [4] C. S. Lent, S. E. Frost, and P. M. Kogge, "Reversible computation with quantum-dot cellular automata (QCA)," in Proceedings of the 2nd conference on Computing frontiers, 25, pp [5] X. Ma, J. Huang, C. Metra, and F. Lombardi, "Reversible gates and testability of one dimensional arrays of molecular QCA," Journal of Electronic Testing, vol. 24, pp , 28. [6] H. Thapliyal and N. Ranganathan, "Conservative qca gate (cqca) for designing concurrently testable

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