ENERGY EFFICIENT DESIGN OF REVERSIBLE POS AND SOP USING URG

Transcription

1 ENERGY EFFICIENT DESIGN OF REVERSIBLE POS AND SOP USING URG Mr.M.Saravanan Associate Professor, Department of EIE Sree Vidyanikethan Engineering College, Tirupati. Dr.K.Suresh Manic Professor & Head, Dept of EEE Sriram Engineering College, Chennai Abstract In this technological world, power consumption is the major criteria in design of digital circuits. The development in the field of nanometer technology leads to minimize the power consumption of logic circuits. Reversible logic design is being one of the promising path gaining greater interest due to less dissipation of heat and low power consumption. In digital circuit design complex logical expressions are easily addressed by POS and SOP architecture. In the contest of designing low power consumption circuits the reversible logic design of POS and SOP become essential. This paper proposes such a design of POS and SOP using Universal Reversible Gate (URG) and Feynman Gate (FG). Keywords: Reversible logic gates, reversible POS, reversible SOP, quantum computing, Low power design. 1. INTRODUCTION as follows section II presents the literature survey on reversible logic gates, section III presents the design of proposed reversible POS and SOP, section IV presents the results analysis of the proposed methods, section V presents the conclusion and future work. 2. LITERATURE SURVEY This section introduces the basics of reversible logic gates and various types of reversible logic gates proposed. Reversible logic has received significant attention in recent years. It has applications in various research areas such as low power CMOS design, optical computing, quantum computing, bioinformatics, thermodynamic technology, DNA computing and nanotechnology. It is not possible to construct quantum circuits without reversible logic gates. Synthesis of reversible logic circuits is significantly more complicated than traditional irreversible logic circuits because in a reversible logic circuit, we are not allowed to use fan-out and feedback [4]. One of the major goals in modern circuit design is reduction of power consumption. As demonstrated by R.Landauer in the early 1960s, irreversible hardware computation, regardless of its realization technique, results in energy dissipation due to the information loss The performance of the reversible circuit based on the [1]. Reversible logic circuits have theoretically zero following parameters internal power dissipation because they do not lose 1. Garbage outputs: The number of unused information. Hence, in 1973, Bennett showed that in outputs present in the reversible logic circuit. order to avoid KTln2 joules of energy dissipation in a 2. Number of reversible logic gates: Total circuit, it must be built using reversible logic gates [2]. number of reversible logic gates used in the A circuit is said to be reversible if the input vector can circuit. be uniquely recovered from the output vector and there 3. Delay: Maximum number of unit delay gates in the path of propagation of inputs to is a one-to-one correspondence between its input and outputs. output assignments, i.e. not only the outputs can be 4. Constant inputs: The number of input which uniquely determined from the inputs, but also the are maintained constant at 0 or 1 in order to inputs can be recovered from the outputs [4-6]. This get the required function. paper presents design of reversible POS and SOP to generate Sum of Product (SOP) and Product of Sum The different types reversible logic gates available is (POS) and also proposes a single circuit to generate all listed below possible minterm and maxterm. The paper is organized ISSN:

2 Reversible logic gates: An (n X n) reversible gate can be represented as[8]: IV = (A,B,C,...) OV = (P,Q,R,...) Where IV and OV are input and output vectors respectively. Table 1 : Existing Reversible Logic Gates Gate Diagrammatic representation Inputs Outputs P, Q Feynman gate A, B Q = A B Toffoli gate A, B, C P,Q, R Q = B R = AB C P,Q, R Fredkin gate A, B, C Q = A B AC R = A C AB P,Q, R Peres gate A, B, C Q = A B R = AB C P,Q, R URG gate A, B, C P = C Q = B AB R =C (A+B) ISSN:

3 P,Q,R,S HNG gate A,B,C,D Q = B R = A B C S = (A B)C AB D ISSN:

4 3. PROPOSED REVERSIBLE DESIGN OF POS AND SOP Designing of reversible logic circuit is a challenging task, since no enough number of gates are available for design. Reversible processor design needs its building blocks should be reversible in this view the designing of reversible POS/SOP become essential one. Digital circuit design becoming more complicated because of development of technology that leads to the need of more components in design. There are two types of general form of Boolean expression for design, they are Product of Sum (POS) and Sum of Product (SOP). 3.1 Product of Sum (POS) Product of Sum is also called as conjuction of maxterms and most of the digital designs are based on this expression. f(a,b) = (0,1,2,3) =(A +B )(A +B)(A+B )(A+B) A maxterm is a sum of literals, in which each input variable appears exactly once, If you have a truth table for a function, you can write a product of maxterms expression by picking out the rows of the table where the function output is Sum of Product (SOP) Sum of Product is also called as disconjuction of minterms and most of the digital designs are based on this expression. f(a,b) = (0,1,2,3) = A B + A B + AB + AB A minterm is a special product of literals, in which each input variable appears exactly once. If you have a truth table for a function, you can write a sum of minterms expression just by picking out the rows of the table where the function output is Implementation of proposed design The circuit is constructed with the help of Feynman Gate (G) gate[7], and URG gate[9]. The truth table of FG gate and URG gate shown Table 3.1 and Table 3.2 respectively. The block diagram of POS and SOP are shown in the figure 3.1 and 3.2 in both the diagram FG gate is used as a NOT function and also to get more fanout for the given input, the URG gate have the facility to provide both AND function and OR function. Hence, for POS implementation URG gate is used as OR plane in first stage followed by AND plane as second stage, in case of SOP implementation URG gate is used as AND plane in first stage followed by OR plane as second stage. There are maximum of 13 garbage outputs (unused outputs) are available in both the design. Table 3.1: truth table of FG gate A B P Q Table 3.2: Truth Table of URG gate A B C P Q R ISSN:

5 Figure 3..1 : Circuit diagram of Reversible POS ISSN:

6 Figure 3.2: Circuit diagram of Reversible SOP Figure 3.3: Circuit diagram of combined Reversible POS/SOP POS/SOP in a single Reversible circuit Figure 3.3 shows the block diagram of reversible circuit which produces both canonical form of expressions POS and SOP as an output This circuit is the optimal design in this scenario, like POS and SOP circuit the first stage is designed with FG gate to provide Complement of input and fan-out for applied input. The second stage consists of URG gate which is designed to provide both minterm and maxterm at 1 st and 3 rd output terminals respectively. The third stage also consists the URG gate to get product and sum of minterm and maxterm respectively. The number of garbages is one of the most important performance parameter in reversible logic design, when the circuit for POS and SOP used individually the number of garbage will be 13 x 2 = 26 but in the proposed combined circuit shown in figure 3.3 the number of garbages is limited to 15. The proposed reversible POS, SOP and POS/SOP are more efficient than the conventional existing circuits. The simulation results of POS, SOP and POS/SOP is shown in figure 4.1(a), 4.1(b) & 4.1(c) the logical behaviour of this proposed design is same as the existing conventional approach. In figure 4.1(a) simulation result of POS, a and b are the input applied, P is the output ie., the product of all existing minterm and s12,s13,s14,s15 produces all possible 2 2 =4 minterm for the applied input a and b. 4. RESULT AND ANALYSIS ISSN:

7 Figure 4.1(a) : Simulation result of POS In figure 4.1(b) simulation result of SOP, a and b are the applied input, P is the output ie., the Sum of all existing maxterms and s12, s13, s14, s15 produces all possible 2 2 =4 maxterms for the applied input a and b. c = AND logic for example if T = 2a+3d then the circuit involves 2numbers of XOR logical operation and 3 numbers of OR logical operations. The performance of the design is based on the number of gate, number of garbage (unused terminals) and number of constants, in this proposed design the above said parameters are optimized to greater extent. In the table it is clear that number of gates needed, the total garbages available are very less in POS/SOP design compared with designing POS and SOP individually. 5. CONCLUSION Figure 4.1(b): simulation result of SOP Figure 4.1(c) shows the simulation result of combined POS/SOP structure, here a and b are the applied inputs, P1 and P2 are the produced output ie, Sum of all existing maxterms and Product of all existing minterms respectively and s12, s14, s16, s18 produces all possible maxterm and s13, s15, s17, s19 produces all possible minterms. This paper has introduced and proposed the reversible logic gates and reversible circuits for realizing different Boolean function with POS, SOP and POS/SOP structures. The proposed design leads to the reduction of power consumption compared with conventional logic circuits and also the existing reversible PLA[15] design, the design proposed is implemented with FG and URG gates only in near future with the invent of new RLG the power consumption may reduced to little more greater extent, not only that there will be a chance of implementing different logic circuits using reversible logic gates and which intern helps to increase the energy efficiency to a greater extent. REFERENCES Figure 4.1(c): Simulation result of POS/SOP But the reversible logic circuits are superior when it is implemented the evaluation of the proposed circuit can be comprehended easily with the help of the Table 3.3. The total logical operation involved in the proposed reversible code converter circuit is calculated with the help of following logical assignments a = NOT logic b = OR logic [1]. Landauer, R., Irreversibility and heat generation in the computing process, IBM J.Research and Development, 5 (3): [2]. Bennett, C.H., Logical reversibility of computation, IBM J. Research and Development, 17: [3]. Kerntopf, P., M.A. Perkowski and M.H.A. Khan,2004. On universality of general reversible multiple valued logic gates, IEEE Proceeding ofthe 34th international symposium on multiple valued logic (ISMVL 04), pp: [4]. Perkowski, M., A. Al-Rabadi, P. Kerntopf, A.Buller, M. Chrzanowska-Jeske, A. Mishchenko, M.Azad Khan, A. Coppola, S. Yanushkevich, V.Shmerko and L. Jozwiak, A general decomposition for reversible logic, Proc. RM 2001, Starkville, pp: Table 3.3: Comparative result of different reversible logic circuits Reversible circuit No. of Gates No. of Garbage No. of Total logical ISSN:

8 Constants calculation POS a+4b+3c SOP a+4c+3b POS/SOP a+7b+7c [10]. Toffoli T., Reversible computing, Tech Memo MIT/LCS/TM-151. MIT Lab for Computer Science. [5]. Perkowski, M. and P. Kerntopf, Reversible Logic. Invited tutorial, Proc. EURO-MICRO, Sept 2001, Warsaw, Poland. [6]. Thapliyal Himanshu, and M.B. Srinivas, 2005.Novel reversible TSG gate and its application for designing reversible carry look ahead adderand other adder architectures, Proceedings of the 10th Asia-Pacific Computer Systems Architecture Conference (ACSAC 05). Lecture Notes of Computer Science, Springer-Verlag, 3740: [7]. Feynman, R., Quantum mechanical computers, Optics News, 11: [8]. Saravanan. M., Cholan K., Abhishek G, Design of Noval Reversible Multiplier Using MKG Gate in Nanotechnology, Proceedings of National Conference on Automation Control and Computing (NCACC-10). [11]. Peres, A., Reversible logic and quantum computers, Physical Review: A, 32 (6): [12]. Azad Khan, Md.M.H., Design of full adder with reversible gate. International Conference on Computer and Information Technology, Dhaka, Bangladesh, pp: [13]. Haghparast, M. and K. Navi, A Novel Reversible Full Adder Circuit for Nanotechnology Based Systems. J. Applied Sci., 7 (24): [14]. Haghparast, M. and K. Navi, Design of a Novel Fault Tolerant Reversible Full Adder ForNanotechnology Based Systems, World Appl. Sci. J., 3 (1): [15] Pradeep Singhla, Naveen Kumar Malik, Reversible Programmable Logic Array (RPLA) using Feynman & Mux gates for lowpower industrial applicationn, ICIAICT 2012 [9]. Mahammad, S.N., Veezhinathan, K Constructing Online Testable Circuits Using Reversible Logic, IEEE Journal of Instrumentation and Measurement, Vol.59, No 1, pp , Jan 2010 ISSN: