Novel Reversible Gate Based Circuit Design and Simulation Using Deep Submicron Technologies

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1 Novel Reversible Gate Based Circuit Design and Simulation Using Deep Submicron Technologies Abstract: The set AND, OR, and EXOR gates are not reversible as Landauer which states that for irreversible logic computations each bit of information lost generates ktln2 joules of heat energy but our main interest lies in reversible computation that arises from the desire to reduce heat dissipation which allows us to gain higher speed and higher densities since the reversible computing determines that whether any previous state of the computation can easily be reconstructed by a given description of the current state. In this paper we have included various simulation results of forward and backward computation of 4x4 reversible TSG( Thapliyal and Srinivas gate) and Fredkin gate which is used to design Four Bit Carry Skip Adder block with 130nm technology that is in deep submicron technology where the adder architecture is designed using seven TSG and one Fredkin gate will be much better optimized as compared to existing Four Bit Carry Skip Adder in terms of low power dissipation. In the implementation of this paper an Electric Tool is used to design the schematic and layout level diagrams of project along with the LT-SPICE Tool and MATLAB/SIMULINK software is used for simulation of the Spice code which tests the functionality of generated layout and schematic blocks. Keywords: Pass transistor Logic, Reversible gate, Reversible adder. 1. INTRODUCTION One of the major goals in VLSI design is to reduce the power dissipation which is demonstrated by R.Landauer in the early 1960s that states the loss of each one bit of information tht dissipates at least KTln2 joules of energy (heat) where the reversible logic is an emerging research area and the main areas of interest in reversible logic is sparked by its applications in several technologies that includes quantum or CMOS or optical and nanotechnology where the reversible implementations are also found in emerging technology such as thermodynamics and adiabatic CMOS which implements the power dissipation in modern technologies is an important issue and overheating is a serious concern for both manufacturer as it is impossible to introducing new and smaller scale technologies with limited temperature range for operating the product and customer needs such as power supply as it is especially important for mobile systems where one of the main benefit of the reversible logic is to bring is theoretically zero power dissipation. B.Vijeta 1, and K.Hemalatha 2 1 M.Tech, Scholar at Aurora's Technological & Research Institute (ATRI), Parvathapur, Hyderabad, A.P., India 2 Assistant professor in department of ECE at Aurora's Technological & Research Institute (ATRI), Parvathapur, Hyderabad, A.P., India A reversible logic gate is an n-input n-output logic device with one-to-one mapping which helps to specify the outputs from the inputs and also the inputs can be uniquely identified and recovered from the outputs which include many parameters for determining the complexity and performance of s. 1. The number of Reversible gates (N) used in. 2. The number of constant inputs (CI) that are to be maintained constant at either 0 or 1 in order to synthesize the given logical function. 3. The number of garbage outputs (GO) refers to the number of unused outputs present in a reversible logic where one cannot avoid the garbage outputs as these are very essential to achieve reversibility. 4. Quantum cost (QC) refers to the cost of the in terms of the cost of a primitive gate which is calculated knowing the number of primitive reversible logic gates (1*1 or 2*2) required to realize the. 2. BASIC REVERSIBLE GATES A reversible logic gate is the one which has always a unique input associated with a unique output and vice versa and the reversible gates never erase any information when they act and consequently a computation based on the reversible logic can be run forward to obtain an answer or the answer is copied and then the whole computation undone to recover all the energy expended apart from the small amount used to copy the answer at the mid-way point. The best example of a reversible logic gate is implementation of the NOT gate as the NOT gate is a 1- input or 1-output gate which simply inverts the bit value it is handed or received where the truth table and icon for the NOT gate is shown in below figure and in table. Figure 1 Not Gate Volume 2, Issue 5 September October 2013 Page 3

2 Table 1 Truth table and symbol for NOT gate Input Output X Z If one knows the output bit value then one can infer the input bit value unambiguously and vice versa. A slightly more complicated example is the 2-input or2-output SWAP gate where the concept of SWAP simply exchanges the bit values it is handed or received by the gate and the truth table and icon for the SWAP gate is shown in below figure and in table. Figure 2 SWAP Gate Table 1 Truth table and symbol for SWAP gate a b a' b' A SWAP operation can be achieved as the result of a sequence of applied fields where the reversible gate of considerable importance in quantum computing is the 2- bit controlled-not gate (CNOT). The truth table and icon for the CNOT gate is shown in below figure and in table where the effect of the controlled - NOT gate is to flip the bit value of the second bit if and only if the first bit is set to Fredkin Gate As per the literature survey done by us states that there can be universal gates for classical irreversible computing such as the NAND gate that has two inputs and one output as there can be universal gates for classical reversible computing and the famous reversible gate is the FREDKIN which is based on the controlled- SWAP gate technology where the truth table and icon for the FREDKIN gate is shown below as the FREDKIN gate can also be seen as a controlled-swap gate in that it swaps the values of the second and third bits, if, and only if, the first bit is set to 1. Table 3 Truth table for FREDKIN gate A B C P Q R Figure 4 symbols for FREDKIN gate 3.2 TSG Gate The proposed reversible TSG gate is shown below where the corresponding truth table of the gate is shown below where it can be easily verified from the Truth Table that the input pattern corresponding to a particular output pattern can be uniquely determined. Figure 3 CNOT gate Table 2 Truth table and symbol for CNOT gate a1 a2 a1' a2' Figure 5 Proposed TSG gate Figure 6 TSG as NOT gate Volume 2, Issue 5 September October 2013 Page 4

3 Figure 7 TSG as XOR gate Figure 9 Four bit Carry Skip Adder Figure 8 TSG as Full Adder Table 4 Truth table for TSG gate A B C D P Q R S DESIGN OF FOUR BIT CARRY SKIP ADDER The interesting adder architecture is carry skip adder where the delay is reduced due to carry computation where in the single bit full adder operation if either input is a logical one where the cell will propagate the carry input to its carry output and therefore, i th full adder carry input C i will propagate to its carry output as C i +1 when and in addition the multiple full adders making a block can generate a block for propagate signals P that provides an alternative path for the incoming carry to the block's carry output signal and the below figure shows a four bit carry skip adder block. F Table 5 Truth table for Single-Bit Addition for full adder A B C in C out S Sum=A B C in Cout= AB + BC in + C in A Generate: C out = 1 independent of C in,g = A B Propagate: C out = C in,p = A B Kill: C out = 0 independent of C in,k = ~A ~B In the proposed solution space for the problem space the carry skip adder block is constructed with seven TSG gates and one Fredkin gate where as it has 4TSG gates that are used as full adder & EXOR gates are used to generate different propagated signals and other 3TSG gates are used for generating the AND4 operation and the Fredkin gate is used to generate a AND & OR operation to generate C out. Figure 10 Block Diagram of 4-bit Carry Skip using TSG and Fredkin gates. Adder Volume 2, Issue 5 September October 2013 Page 5

4 4. SIMULATION RESULTS The below are the figures represents the design of the proposed system and their yielded results using the LT- SPICE Tool and Matlab/Simulink software: Figure 11 Layout of Fredkin Gate Figure 13 Layout of TSG Gate Figure 12 schematic of Fredkin Gate Figure 14 schematic of TSG Gate Figure 12 Simulation results of Fredkin Gate Figure 15 Simulation results of TSG Gate Volume 2, Issue 5 September October 2013 Page 6

5 is much better optimized when compared to existing reversible gates designs as shown in table below. Table 6 Gates usage summery METHOD GATES USED POWER DISSIPATION Proposed 7TSG,1Fredkin *10^-9 Existing 7TSG,1Fredkin *10^-3 Existing 4TSG,4Fredkin Existing 4TSG,3Toffili, 1Fredkin Figure 16 Layout of 4-bit Carry Skip Adder. Figure 17 schematic of 4-bit Carry Skip Adder. REFERENCES [1] ASIC Physical Design CMOS Processes, Smith Text-Chapters 2&3,Weste- CMOS VLSI Design. [2] VLSI Digital Circuits, Mary Jane Irwin, Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al. [3] VLSI Design Rules, Joseph Nahas, Peter Kogge University of Notre Dame, [4] Transistor Realization of Reversible TSG Gate and Reversible Adder Architecture, Himanshu Thapliyal and A.P Vinod, Circuits and Systems (APCCAS),Singapore. [5] Optimal Design of A Reversible Full Adder, University Gent and Imec v.z.w., vakgroep elektronica, Sint Pietersnieuwstraat 41, B Gent, Belgium. AUTHOR B.VIJETA has completed her B.tech degree in Electronics & Communication Eng in 2006 from TPIST affiliated to JNTUH University, A.P, India and presently she is pursuing her M.Tech degree in VLSI-SD at Aurora s Technological and Research Institute, Parvathapur, Uppal, Andhra Pradesh, India. Figure 18 Simulation results of 4-bit Carry Skip Adder. 5. CONCLUSION Thus by using seven TSG & one Fredkin gate for designing 4-bit Carry Skip adder, low power dissipation K.HEMALATHA has completed her M.TECH degree in 2012 and her B.Tech Degree in 2008 in Electronics and Communication Eng from JNTUH university, A.P, India and presently she is working as Assistant Professor in department of ECE at Aurora s Technological & Research Institute, Parvathapur, Uppal, Andhra Pradesh, India. Her interests are in the areas of DSD, ECA, DFTS, STLD. Volume 2, Issue 5 September October 2013 Page 7