Analysis of Multiplier Circuit Using Reversible Logic

Transcription

1 IJIRST International Journal for Innovative Research in Science & Technology Volume 1 Issue 6 November 2014 ISSN (online): Analysis of Multiplier Circuit Using Reversible Logic Vijay K Panchal PG Student Electronics & Communication Department Silver Oak College of Engineering & Technology, Ahmedabad (INDIA) Vimal H Nayak Assistant Professor Electronics & Communication Department Silver Oak College of Engineering & Technology, Ahmedabad (INDIA) Abstract Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. Reversible circuits hold promise in futuristic computing technologies like low power VLSI, quantum computing, nanotechnology, optical computing etc. Reversible gates require constant inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. It is important to minimize parameters such as constant and garbage bits, quantum cost and delay in the design of reversible circuits. In this paper, new multiplier using Toffoli gate, Peres gate, Double Peres gate is proposed for minimization of constant input, garbage output, quantum cost. Keywords: Reversible Logic Gate, Constant Input Garbage Output, Quantum Cost, Low-power VLSI, Nanotechnology. I. INTRODUCTION Energy dissipation is most important factor in VLSI design. Reversible logic has received great attention in the recent years as it ensures low energy dissipation. In 1961, Landauer had shown that during irreversible computation 1 bit of information lost results in KTln2 Joules of energy dissipation. Irreversible circuits dissipate KTln2 joules of energy for each bit of information lost where K = 1.38 joules kelvin -1 is Boltzmann constant and T is the temperature at which computation is done [1]. In 1973 Bennet proved that this KTln2 joule of energy dissipation will not occur if computation is performed in a reversible manner where number of input and output vectors must be same and each input output pattern must be unique [2]. So, Reversible logic gates avoid loss of bit in computation. Reversible logic gate generates a permutation of input vectors. A k x k reversible gate uniquely maps k input vectors to k output vectors. There has one-to-one correspondence between them. A circuit is said to be reversible if the input vector can be uniquely determined from the output vector and there is a one-to-one correspondence between its input and output assignments, i.e. not only the outputs can be uniquely determined from the inputs but also the inputs can be recovered from the outputs. Thus, the number of inputs and outputs in reversible logic circuits (gates) are equal. Such circuits (gates) allow the reproduction of the inputs from observed outputs and we can recover the inputs from the outputs. In Reversible circuit, following parameters are calculated for comparison of different circuits: [3], [4] of Gates (N): The number of reversible gates used in circuit. of Constant inputs (CI): This refers to the number of inputs that are to be maintained constant at either 0 or 1 in order to synthesize the given logical function. of Garbage Outputs (GO): This refers to the number of unused outputs present in a reversible logic circuit. One cannot avoid the garbage outputs as these are very essential to achieve reversibility. Quantum Cost (QC): This refers to the cost of the circuit in terms of the cost of a primitive gate. It is calculated knowing the number of primitive reversible logic gates (1x1 or 2x2) required to realize the circuit. The Design constrains for reversible logic gate are minimized above parameters and fan-out is not allowed. In this paper, a 4x4 multiplier using reversible gate is proposed. Section II included some basic gates which is used in proposed multiplier circuit. Section III included proposed multiple with its evaluation. In Section IV, result and comparison with existing design is given. At last, Conclusion and reference are included. II. REVERSIBLE LOGIC GATE An n x n reversible gate can be represented as: IV = (I1, I2, I3 In) OV = (O1, O2, O3 On) Where IV and OV are input and output vectors respectively. Several reversible gates have been proposed. Each reversible gate has a cost associated with it called the quantum cost. The quantum cost of a reversible gate is the number of 1x1 and 2x2 reversible gates or quantum logic gates required in its design. All rights reserved by 279

2 A. The Feynman Gate The Feynman gate (FG) or the Controlled-NOT gate (CNOT) is a 2 inputs 2 outputs reversible gate having the mapping (A, B) to (P=A, Q=A B) where A, B are the inputs and P, Q are the outputs, respectively [5]. Since it is a 2x2 gate, it has a quantum cost of 1. Figures 1(a) and 1(b) show the block diagrams and quantum representation of the Feynman gate. (a)the Feynman gate (b) Quantum representation of the Feynman gate Fig. 1: Feynman gate and its quantum implementation B. The Peres Gate Figure 2.4 shows a 3*3 Peres gate. The input vector is I (A, B, C) and the output vector is O (P, Q, and R). The output is defined by P = A, Q = A B and R = (A.B) C). Quantum cost of a Peres gate is four [7]. A P = A A P = A B PG Q = A B B Q =A B C (a)peres Gate R = (A.B) C C V V + V (b) Quantum representation of the Peres Gate Fig. 2: Peres Gate and its Quantum implementation R=(A.B) C) C. The Toffoli Gate Toffoli Gate is 3x3 reversible gate with three inputs and three outputs. The inputs (A, B, C) mapped to the outputs (P = A, Q = B, R = (A.B) C) is as shown in the figure 2.6. Its truth table is shown in Table 2.3.Toffoli gate is one of the most popular reversible gates and has quantum cost of five [3]. (a) Toffoli Gate (b) Quantum implementation of Toffoli Gate Fig. 3: Toffoli Gate and its Quantum implementation D. The Double Peres Gate The Double Peres Gate (DPG) is 4x4 reversible Gate with four inputs and four outputs. The inputs (A, B, C, D) mapped to (P = A, Q = A B, R = A B D, S = (A B) D A.B C) is as shown in figure 4. Quantum cost is six [8]. All rights reserved by 280

3 (a)the Double Peres Gate (b) Quantum implementation of Double Peres Gate Fig. 4: The Double Peres Gate, its Quantum implementation III. PROPOSED MULTIPLIER USING REVERSIBLE LOGIC GATE The operation of a 4x4 reversible multiplier is shown in Fig 3.1. It consists of 16 Partial product bits of the X and Y inputs to perform 4 x 4 multiplications. However, it can extend to any other N x N reversible multiplier. The design of the proposed multiplier uses parallel multiplier is done using two steps. Part I: Partial Product Generation (PPG) Part II: Multi-Operand Addition (MOA) In partial product generation, product of each bit of multiplicand to multiplier is generated. In multi-operand addition, Carry save adder is used for addition of 4 bit and later carry propagation adder is used. Partial Product Generation ( PPG ) X3 X2 X1 X0 Y3 Y2 Y1 Y0 P03 P02 P01 P00 Multi Operand Addition (MOA) P13 P12 P11 P10 P23 P22 P21 P20 P33 P32 P31 P30 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 Fig. 5: Basic operation of 4x4 Multiplier A. Partial Product Generation In Partial Product Generation (PPG), total sixteen products are generated. It is indicated as P ji = X i *Y j, where X i is i th bit of multiplicand and Y j is j th bit of multiplier. Partial Product Generation using 7 Peres gate and 9 Toffoli gate is shown in fig.6. These both gates can generate product but Toffoli gate is also generate copy bits of input bits. Quantum costs of these gates are 4 and 5 respectively. Here note that 7 Peres gate is used for minimization of Quantum cost of circuit as in generation of P03, P13, P23, P33, P30, P31, P32 use of Toffoli gate and Peres gate does not make difference in functioning. These sixteen partial products are used in next section of Multi-operand-addition (MOA). The garbage output is shown as G in fig.7. All rights reserved by 281

4 Fig. 6: Proposed Partial Product Generation (PPG) using Toffoli Gate (TG) and Peres Gate (PG) B. Multi-Operand Addition (MOA) In Multi-operand Addition, sixteen partial products are taken as inputs and eight bit output as answer of multiplier is generated. Here, eight full adder and four half adder is required The basic cells for such a multiplier is full adder using Double Peres Gate with three inputs and one constant input, two garbage outputs and half adder using Peers Gate with two inputs and one constant input, one garbage output. Quantum cost of Double Peres gate and Peres gate are 6 and 4 respectively. The fig.7 shows Multi-operand Addition using Double Peres gate and Peres gate. All rights reserved by 282

5 Fig. 7: Multi-Operand Addition (MOA) Using Double Peres Gate (DPG) and Peres Gate (PG) Table 1 shows performance parameter of proposed Multiplier. of gates (N), of constant inputs (CI) and of garbage output can easily found form figure 3.2 and 3.3..In Partial Product Generation (PPG), 7 Peres gate (PG) and 9 Toffoli gate (TG) is used which has quantum cost (QC) 5. In Multi-Operand Addition (MOA), 8 Double Peres gate (DPG) and 4 Peres gate (PG) is used. The quantum cost (QC) of Double Peres gate (DPG) and Peres gate (PG) is 6 and 4 respectively. Table 1 Evaluation of the Proposed Multiplier of Reversible gates of Constant inputs of Garbage outputs Quantum cost QC PPG MOA Multiplier N CI GO IV. RESULT AND COMPARISON The proposed m u l t i p l i e r circuit is more efficient than the existing circuits presented in [9], [10], [11], [12] and [13]. Evaluation can be comprehended easily with the help of the comparative results in Table 2. One of the main factors of a circuit is its hardware complexity. We can prove that our proposed circuits are better than the existing approaches in term of hardware complexity. Let, α = A two input EX-OR gate calculation All rights reserved by 283

6 β = A two input AND gate calculation δ = A NOT calculation T= Total logical calculation Total logical calculation is the count of the XOR, AND, NOT logic in the output expressions. For example, PG has two XORs and one AND in the output expressions. Therefore: T (TG) = 1α+1β, T (PG) = 2α+1β, T (DPG) = 6α+2β. So, Total logical calculation T equals to 9 (1α+1β) + 11 (2α+1β) + 8(6α+2β) = 79α+36β. Table - 2 Comparison of Reversible multiplier of of of Total GarbageQuantum cost Reversible ReversibleConstant Logical Calculation outputs Multiplier gates inputs T QC N GO CI TSG[13] α+103β +71 δ MKG[12] α+52β +36 δ PFAG[11] α+44β BVF[10] α+36β RAM[9] α+36β Proposed α+36β V. CONCLUSION In this paper, multiplier circuit is presented. Table 2 demonstrates that the proposed reversible multipliers are better than the existing designs in term of hardware complexity, number of gates, garbage outputs, constant inputs, and total quantum cost. Proposed reversible multiplier circuits can be applied to the design of complex systems in nanotechnology. As future work, some other techniques to reduce the garbage outputs and constant inputs might be possible. In addition, some other optimization techniques such as genetic algorithm may be used to reduce the quantum cost of the circuit. REFERENCES [1] R. Landauer, Irreversibility and heat generation in the computing process, IBM Journal of Research Development, 5 (3) (1961) [2] C.H. Bennett, Logical reversibility of computation, IBM Journal of Research Development, 17 (1973) [3] T. Toffoli., Reversible Computing, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980). [4] E. Fredkin and T. Toffoli, Conservative logic, Int l J. Theoretical Physics, Vol. 21, pp , [5] R. Feynman, Quantum Mechanical Computers, Optics News, Vol.11, pp , [6] B. Parhami; Fault Tolerant Reversible Circuits Proc. 40th Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA, Oct [7] A. Peres, Reversible Logic and Quantum Computers, Physical review A, 32: , [8] W. N. N. Hung, X. Song, G. Yang, J. Yang and M. Perkowski, Quantum Logic Synthesis by Symbolic Reachability Analysis, Proc. 41st annual conference on Design automation DAC, pp , January [9] Rangaraju H G, Aakash Babu Suresh, Muralidhara K N, Design and Optimization of Reversible Multiplier Circuit, International Journal of Computer Applications ( ) Volume 52 No.10, August 2012 [10] H R Bhagyalakshmi and M K Venkatesha, An Improved Design of a Multiplier using Reversible Logic Gates. International Journal of Engineering Science and Technology, vol. 2(8), pp [11] M S Islam, M M Rahman, Z Begum and M Z Hafiz, Low Cost Quantum Realization of Reversible Multiplier Circuit. Information Technology Journal, vol. 8(2), pp [12] M. Shams, M. Haghparast and K. Navi, Novel Reversible Multiplier Circuit in Nanotechnology, World Applied Science Journal Vol. 3, No. 5, pp , [13] H. Thapliyal and M.B. Srinivas, Novel Reversible Multiplier Architecture Using Reversible TSG Gate, Proc. IEEE International Conference on Computer Systems and Applications, pp , March [14] M. Haghparast, S. Jafarali Jassbi, K. Navi and O. Hashemipour, Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology, World Applied Science Journal Vol. 3 No. 6, pp , [15] M.S. Islam et al., Low cost quantum realization of reversible multiplier circuit, Information technology journal, 8 (2009) 208. All rights reserved by 284