# Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker

Size: px
Start display at page:

Transcription

1 Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker Note: + implies OR,. implies AND, ~ implies NOT Question 1: a) (4%) Use transmission gates to design a 3-input OR gate Note: There are other solutions as well which use the same number of transistors.

2 b) (11%) Now use transmission gates to construct the following function: F = (A+B+C).(D+E) The maroon circle is A+B+C. This is fed to the top un-circled transmission gate with positive control input = D+E (yellow circle) and negative control input = ~(D+E) = ~D.~E (green circle). The 2 un-circled transmission gates form a 2-input AND to realize Out = (A+B+C).(D+E)

3 Question 2: a) (11%) Use transmission gates to design a multiplexer with select signals S0, S1, inputs A, B, C, D, and output Out. You can arrange the signals in any way you want. One implementation is as follows: S1 S0 Out 0 0 A 0 1 B 1 0 C 1 1 D

4 b) (4%) Now suppose input A is always logic 0 and B is always logic 1. Can you make the circuit simpler? Only an NMOS is required to transmit a 1 and only a PMOS to transmit a 0. So we can eliminate a couple of transistors:

5 Question 3: Consider the function: X = A.B.C.D + E.F.G.H a) (4%) Draw its logic gate diagram using negative gates only (NAND, NOR, INV) b) (8%) Draw the stick diagram of each unique gate you have used above (i.e. if you have used 2 gates of the same type, just draw the stick diagram once) 4-input NAND 2-input NAND

6 c) (5%) Draw a compound gate transistor level diagram of X

7 Question 4: a) (4%) Suppose you have a design constraint that your gates can have a maximum of 2 inputs. Redraw the logic gate diagram of X using negative gates only. This is a tricky problem. Assuming complement signals like ~A are not available, this is the solution: But if complement signals are available, there is a slightly simpler solution:

8 b) (6%) Redraw the logic gate diagram of X using positive gates only (AND, OR) and the same constraint - gates can have a maximum of 2 inputs. Notice that a 4-input AND gate can be directly decomposed into a cascade of two 2-input AND gates followed by another AND gate. That s because it s a positive gate. The same cannot be done with negative gates.

9 Question 5: a) (3%) Show the truth table for a 2-input XOR gate and give its logic equation: A XOR B =? A XOR B = A.~B + ~A.B A B A XOR B b) (10%) A 3-bit parity checker counts the number of 1 s in a sequence of 3 bits and outputs 1 if odd, 0 if even. (Example: If the input is 101, output is 0, but if the input is 001, output is 1). Design this circuit using negative gates only and draw the transistor level diagram. You can assume that negative inputs like ~A are available. A B C Out The truth table outputs logic 1 in 4 cases. Combining these terms, we can write: Out = ~A.~B.C + ~A.B.~C + A.~B.~C + A.B.C In general, any XOR gate outputs logic 1 if the total number of input 1 s are odd, otherwise it outputs logic 0. So a 3-bit parity checker is simply a 3-input XOR gate: (A XOR B) XOR C = (A.~B + ~A.B).~C + ~(A.~B + ~A.B).C This eventually simplifies to the above expression for Out.

10 ~

11 Question 6: (10%) Consider the following 2-to-1 MUX built using transmission gates as shown in class. The ~pickx signal is generated from an inverter which has a delay of 2 time units. Look at the given timing diagram and draw the waveform for Out from beginning to end. Is there any period of time when Out isn t well defined? Due to the 2 unit inverter delay, both the transmission gates are ON during these time periods: 10-12, 20-22, For the first 2 cases, both inputs are the same and there is no conflict. For 30-32, both pickx and ~pickx are logic 0, so both PMOS are conducting and there is a conflict between X and Y. You might expect X to win the conflict because PMOS can pass strong 1 s and weak 0 s. Actually we don t know what happens. Since the Out signal might be driving other parts of the circuit, we should never allow such a glitch or undefined state to occur.

12 Question 7: (20%) Design a latch with: Inputs = D, Clock, Set, Reset Output = ~Q Active-high asynchronous Reset Active-high synchronous Set This means that: Reset Clock Set ~Q 1 Don t care Don t care Load new ~D 0 0 Don t care Retain previous ~Q Notice the basic structure of the latch transmission gate followed by a loop consisting of 2 negative gates and a transmission gate. The NAND is added inside the loop to ensure Asynchronous Reset, while the OR outside the loop implements Synchronous Set. Note: Set sets output Q to 1, that s why ~Q is 0. Similarly Reset should make Q = 0, so ~Q = 1. Note: Generally positive gates like OR aren t recommended. It s better to replace them with negative logic depending on the technology/circuits used.

### UNIVERSITI TENAGA NASIONAL. College of Information Technology

UNIVERSITI TENAGA NASIONAL College of Information Technology BACHELOR OF COMPUTER SCIENCE (HONS.) FINAL EXAMINATION SEMESTER 2 2012/2013 DIGITAL SYSTEMS DESIGN (CSNB163) January 2013 Time allowed: 3 hours

### ECE 2300 Digital Logic & Computer Organization

ECE 23 Digital Logic & Computer Organization Spring 28 Combinational Building Blocks Lecture 5: Announcements Lab 2 prelab due tomorrow HW due Friday HW 2 to be posted on Thursday Lecture 4 to be replayed

### Topics. CMOS Design Multi-input delay analysis. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

Topics CMO Design Multi-input delay analysis pring 25 Transmission Gate OUT Z OUT Z pring 25 Transmission Gate OUT When is low, the output is at high impedance When is high, the output follows However,

### Additional Gates COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

Additional Gates COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Additional Gates and Symbols Universality of NAND and NOR gates NAND-NAND

### Sequential vs. Combinational

Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current

### XOR - XNOR Gates. The graphic symbol and truth table of XOR gate is shown in the figure.

XOR - XNOR Gates Lesson Objectives: In addition to AND, OR, NOT, NAND and NOR gates, exclusive-or (XOR) and exclusive-nor (XNOR) gates are also used in the design of digital circuits. These have special

### EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html

### Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Digital Logic

Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Digital Logic Our goal for the next few weeks is to paint a a reasonably complete picture of how we can go from transistor

### ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes

### Synchronous Sequential Circuit

Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait

### Logic. Combinational. inputs. outputs. the result. system can

Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends

### MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

DEPARTMENT: ECE MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 QUESTION BANK SUBJECT NAME: DIGITAL ELECTRONICS UNIT : Design of Sequential Circuits PART A ( Marks). Draw the logic diagram 4: Multiplexer.(AUC

### Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of

### UNIT 8A Computer Circuitry: Layers of Abstraction. Boolean Logic & Truth Tables

UNIT 8 Computer Circuitry: Layers of bstraction 1 oolean Logic & Truth Tables Computer circuitry works based on oolean logic: operations on true (1) and false (0) values. ( ND ) (Ruby: && ) 0 0 0 0 0 1

### CSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid

CSE140: Components and Design Techniques for Digital Systems Midterm Information Instructor: Mohsen Imani Midterm Topics In general: everything that was covered in homework 1 and 2 and related lectures,

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization

### Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible

### ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

### Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits - 1 guntzel@inf.ufsc.br

### CMPEN 411. Spring Lecture 18: Static Sequential Circuits

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 18: Static Sequential Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11

### EE115C Digital Electronic Circuits Homework #4

EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors

### BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO

UN IVERSIT Y O F CA LIFO RNI A AT BERKELEY BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO SAN TA BARBA RA S AN TA CRUZ De p a r tm en t of Ele ctr i ca l En gin e e rin g a

### LECTURE 28. Analyzing digital computation at a very low level! The Latch Pipelined Datapath Control Signals Concept of State

Today LECTURE 28 Analyzing digital computation at a very low level! The Latch Pipelined Datapath Control Signals Concept of State Time permitting, RC circuits (where we intentionally put in resistance

### Time Allowed 3:00 hrs. April, pages

IGITAL ESIGN COEN 32 Prof. r. A. J. Al-Khalili Time Allowed 3: hrs. April, 998 2 pages Answer All uestions No materials are allowed uestion a) esign a half subtractor b) esign a full subtractor c) Using

### ELEN Electronique numérique

ELEN0040 - Electronique numérique Patricia ROUSSEAUX Année académique 2014-2015 CHAPITRE 3 Combinational Logic Circuits ELEN0040 3-4 1 Combinational Functional Blocks 1.1 Rudimentary Functions 1.2 Functions

### MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 DEPARTMENT: EEE QUESTION BANK SUBJECT NAME: DIGITAL LOGIC CIRCUITS SUBJECT CODE: EE55 SEMESTER IV UNIT : Design of Synchronous Sequential Circuits PART

### EE 209 Logic Cumulative Exam Name:

EE 209 Logic Cumulative Exam Name: 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines: true / false b.) An 8-to-1 mux and no other logi can be

### School of Computer Science and Electrical Engineering 28/05/01. Digital Circuits. Lecture 14. ENG1030 Electrical Physics and Electronics

Digital Circuits 1 Why are we studying digital So that one day you can design something which is better than the... circuits? 2 Why are we studying digital or something better than the... circuits? 3 Why

### Different encodings generate different circuits

FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,

### UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown

### Computers also need devices capable of Storing data and information Performing mathematical operations on such data

Sequential Machines Introduction Logic devices examined so far Combinational Output function of input only Output valid as long as input true Change input change output Computers also need devices capable

vidyarthiplus.com vidyarthiplus.com vidyarthiplus.com ANNA UNIVERSITY- COMBATORE B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009. ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER DIGITAL LOGIC CIRCUITS PART-A

### Sample Test Paper - I

Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:

### Chapter 2 Combinational Logic Circuits

Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 3 Additional Gates and Circuits Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in

### EECS 270 Midterm 2 Exam Answer Key Winter 2017

EES 270 Midterm 2 Exam nswer Key Winter 2017 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. NOTES: 1. This part of the exam

### Fundamentals of Digital Design

Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric

### EECS150 - Digital Design Lecture 23 - FSMs & Counters

EECS150 - Digital Design Lecture 23 - FSMs & Counters April 8, 2010 John Wawrzynek Spring 2010 EECS150 - Lec22-counters Page 1 One-hot encoding of states. One FF per state. State Encoding Why one-hot encoding?

### Homework Assignment #3 EE 477 Spring 2017 Professor Parker , -.. = 1.8 -, 345 = 0 -

Homework Assignment #3 EE 477 Spring 2017 Professor Parker Note:! " = \$ " % &' ( ) * ),! + = \$ + % &' (, *,, -.. = 1.8 -, 345 = 0 - Question 1: a) (8%) Define the terms V OHmin, V IHmin, V ILmax and V

### Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 23rd, 2007 Total Time = 90 Minutes, Total

### MODULAR CIRCUITS CHAPTER 7

CHAPTER 7 MODULAR CIRCUITS A modular circuit is a digital circuit that performs a specific function or has certain usage. The modular circuits to be introduced in this chapter are decoders, encoders, multiplexers,

### Karnaugh Maps (K-Maps)

Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC

### CS61C : Machine Structures

CS 61C L15 Blocks (1) inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks Outline CL Blocks Latches & Flip Flops A Closer Look 2005-07-14 Andy Carle CS

### Gates and Flip-Flops

Gates and Flip-Flops Chris Kervick (11355511) With Evan Sheridan and Tom Power December 2012 On a scale of 1 to 10, how likely is it that this question is using binary?...4? What s a 4? Abstract The operation

### DE58/DC58 LOGIC DESIGN DEC 2014

Q.2 a. In a base-5 number system, 3 digit representations is used. Find out (i) Number of distinct quantities that can be represented.(ii) Representation of highest decimal number in base-5. Since, r=5

### Digital Logic. Lecture 5 - Chapter 2. Outline. Other Logic Gates and their uses. Other Logic Operations. CS 2420 Husain Gholoom - lecturer Page 1

Lecture 5 - Chapter 2 Outline Other Logic Gates and their uses Other Logic Operations CS 2420 Husain Gholoom - lecturer Page 1 Digital logic gates CS 2420 Husain Gholoom - lecturer Page 2 Buffer A buffer

### WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of

27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics Number Systems and Codes T : Solution Converting into decimal number system 2 + 3 + 5 + 8 2 + 4 8 +

### CS61C : Machine Structures

inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks 2005-07-14 CS 61C L15 Blocks (1) Andy Carle Outline CL Blocks Latches & Flip Flops A Closer Look CS

### Computer organization

Computer organization Levels of abstraction Assembler Simulator Applications C C++ Java High-level language SOFTWARE add lw ori Assembly language Goal 0000 0001 0000 1001 0101 Machine instructions/data

### Simulation of Logic Primitives and Dynamic D-latch with Verilog-XL

Simulation of Logic Primitives and Dynamic D-latch with Verilog-XL November 30, 2011 Robert D Angelo Tufts University Electrical and Computer Engineering EE-103 Lab 3: Part I&II Professor: Dr. Valencia

### DIGITAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Computers 2 LOGIC GATES

### Floating Point Representation and Digital Logic. Lecture 11 CS301

Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8

### Show that the dual of the exclusive-or is equal to its compliment. 7

Darshan Institute of ngineering and Technology, Rajkot, Subject: Digital lectronics (2300) GTU Question ank Unit Group Questions Do as directed : I. Given that (6)0 = (00)x, find the value of x. II. dd

### ECE 342 Electronic Circuits. Lecture 34 CMOS Logic

ECE 34 Electronic Circuits Lecture 34 CMOS Logic Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 De Morgan s Law Digital Logic - Generalization ABC... ABC...

### Lecture 7: Logic design. Combinational logic circuits

/24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic

### EE 209 Spiral 1 Exam Solutions Name:

EE 29 Spiral Exam Solutions Name:.) Answer the following questions as True or False a.) A 4-to- multiplexer requires at least 4 select lines: true / false b.) An 8-to- mux and no other logic can be used

### Chapter 2: Boolean Algebra and Logic Gates

Chapter 2: Boolean Algebra and Logic Gates Mathematical methods that simplify binary logics or circuits rely primarily on Boolean algebra. Boolean algebra: a set of elements, a set of operators, and a

### EECS150 - Digital Design Lecture 25 Shifters and Counters. Recap

EECS150 - Digital Design Lecture 25 Shifters and Counters Nov. 21, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy of Prof. John

### Homework Assignment #5 EE 477 Spring 2017 Professor Parker

Homework Assignment #5 EE 477 Spring 2017 Professor Parker Question 1: (15%) Compute the worst-case rising and falling RC time constants at point B of the circuit below using the Elmore delay method. Assume

### Textbook: Digital Design, 3 rd. Edition M. Morris Mano

: 25/5/ P-/70 Tetbook: Digital Design, 3 rd. Edition M. Morris Mano Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter 3 25/5/ P-2/70 Chapter 3 Gate-Level Minimization

### Dynamic Combinational Circuits. Dynamic Logic

Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:

### CPE100: Digital Logic Design I

Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm02 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Nov. 16 th In normal lecture (13:00-14:15)

### Vidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution

S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should

### Digital Logic Appendix A

Digital Logic Appendix A Boolean Algebra Gates Combinatorial Circuits Sequential Circuits 1 Boolean Algebra George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 Describe digital circuitry

### CHW 261: Logic Design

CHW 26: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Digital Fundamentals Digital Concepts Slide 2 What?

### Synchronous Sequential Logic

1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in

### Lecture 4: Implementing Logic in CMOS

Lecture 4: Implementing Logic in CMOS Mark Mcermott Electrical and Computer Engineering The University of Texas at ustin Review of emorgan s Theorem Recall that: () = + and = ( + ) (+) = and + = ( ) ()

### Part 1: Digital Logic and Gates. Analog vs. Digital waveforms. The digital advantage. In real life...

Part 1: Digital Logic and Gates Analog vs Digital waveforms An analog signal assumes a continuous range of values: v(t) ANALOG A digital signal assumes discrete (isolated, separate) values Usually there

### Counters. We ll look at different kinds of counters and discuss how to build them

Counters We ll look at different kinds of counters and discuss how to build them These are not only examples of sequential analysis and design, but also real devices used in larger circuits 1 Introducing

### Binary addition (1-bit) P Q Y = P + Q Comments Carry = Carry = Carry = Carry = 1 P Q

Digital Arithmetic In Chapter 2, we have discussed number systems such as binary, hexadecimal, decimal, and octal. We have also discussed sign representation techniques, for example, sign-bit representation

### Quiz 2 Solutions Room 10 Evans Hall, 2:10pm Tuesday April 2 (Open Katz only, Calculators OK, 1hr 20mins)

UNIVERSITY OF CALIFORNIA AT BERKELEY ERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO SANTA BARBARA SANTA CRUZ Department of Electrical Engineering and Computer Sciences Quiz 2 Solutions

### Hakim Weatherspoon CS 3410 Computer Science Cornell University

Hakim Weatherspoon CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. memory inst 32 register

### Implementation of Boolean Logic by Digital Circuits

Implementation of Boolean Logic by Digital Circuits We now consider the use of electronic circuits to implement Boolean functions and arithmetic functions that can be derived from these Boolean functions.

### Unit 2 Session - 6 Combinational Logic Circuits

Objectives Unit 2 Session - 6 Combinational Logic Circuits Draw 3- variable and 4- variable Karnaugh maps and use them to simplify Boolean expressions Understand don t Care Conditions Use the Product-of-Sums

### Computer Organization: Boolean Logic

Computer Organization: Boolean Logic Representing and Manipulating Data Last Unit How to represent data as a sequence of bits How to interpret bit representations Use of levels of abstraction in representing

### 3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value

EGC22 Digital Logic Fundamental Additional Practice Problems. Complete the following table of equivalent values. Binary. Octal 35.77 33.23.875 29.99 27 9 64 Hexadecimal B.3 D.FD B.4C 2. Calculate the following

### MOSIS REPORT. Spring MOSIS Report 1. MOSIS Report 2. MOSIS Report 3

MOSIS REPORT Spring 2010 MOSIS Report 1 MOSIS Report 2 MOSIS Report 3 MOSIS Report 1 Design of 4-bit counter using J-K flip flop I. Objective The purpose of this project is to design one 4-bit counter

### EECS150 - Digital Design Lecture 17 - Sequential Circuits 3 (Counters)

EECS150 - Digital Design Lecture 17 - Sequential Circuits 3 (Counters) March 19&21, 2002 John Wawrzynek Spring 2002 EECS150 - Lec13-seq3 version 2 Page 1 Counters Special sequential circuits (FSMs) that

### Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution

. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)

### Name: Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015

University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values

### EECS150 - Digital Design Lecture 11 - Shifters & Counters. Register Summary

EECS50 - Digital Design Lecture - Shifters & Counters February 24, 2003 John Wawrzynek Spring 2005 EECS50 - Lec-counters Page Register Summary All registers (this semester) based on Flip-flops: q 3 q 2

### The Design Procedure. Output Equation Determination - Derive output equations from the state table

The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flipflop types

### EECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs. Cross-coupled NOR gates

EECS150 - Digital Design Lecture 23 - FFs revisited, FIFOs, ECCs, LSFRs April 16, 2009 John Wawrzynek Spring 2009 EECS150 - Lec24-blocks Page 1 Cross-coupled NOR gates remember, If both R=0 & S=0, then

### CMPE12 - Notes chapter 1. Digital Logic. (Textbook Chapter 3)

CMPE12 - Notes chapter 1 Digital Logic (Textbook Chapter 3) Transistor: Building Block of Computers Microprocessors contain TONS of transistors Intel Montecito (2005): 1.72 billion Intel Pentium 4 (2000):

### University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: S. Brown,

### Logic Gate Level. Part 2

Logic Gate Level Part 2 Constructing Boolean expression from First method: write nonparenthesized OR of ANDs Each AND is a 1 in the result column of the truth table Works best for table with relatively

### Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary

Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION

### CHAPTER 7. Exercises 17/ / /2 2 0

CHAPTER 7 Exercises E7. (a) For the whole part, we have: Quotient Remainders 23/2 /2 5 5/2 2 2/2 0 /2 0 Reading the remainders in reverse order, we obtain: 23 0 = 0 2 For the fractional part we have 2

### Boolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions?

Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits Other operations NAND A NAND B = NOT ( A ANDB) = AB NOR A NOR B = NOT ( A ORB) = A + B Truth tables What is the result of the operation

### Unit 3 Session - 9 Data-Processing Circuits

Objectives Unit 3 Session - 9 Data-Processing Design of multiplexer circuits Discuss multiplexer applications Realization of higher order multiplexers using lower orders (multiplexer trees) Introduction

### Written exam with solutions IE1204/5 Digital Design Friday 13/

Written eam with solutions IE204/5 Digital Design Friday / 207 08.00-2.00 General Information Eaminer: Ingo Sander. Teacher: Kista, William Sandqvist tel 08-7904487 Teacher: Valhallavägen, Ahmed Hemani

### Design of Sequential Circuits

Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable

### Written exam for IE1204/5 Digital Design with solutions Thursday 29/

Written exam for IE4/5 Digital Design with solutions Thursday 9/ 5 9.-. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 8-794487 Exam text does not have to be returned when

### Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design

### Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic

### University of Minnesota Department of Electrical and Computer Engineering

University of Minnesota Department of Electrical and Computer Engineering EE2301 Fall 2008 Introduction to Digital System Design L. L. Kinney Final Eam (Closed Book) Solutions Please enter your name, ID

### Lecture 16: Circuit Pitfalls

Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004 Outline Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution

### In Module 3, we have learned about Exclusive OR (XOR) gate. Boolean Expression AB + A B = Y also A B = Y. Logic Gate. Truth table

Module 8 In Module 3, we have learned about Exclusive OR (XOR) gate. Boolean Expression AB + A B = Y also A B = Y Logic Gate Truth table A B Y 0 0 0 0 1 1 1 0 1 1 1 0 In Module 3, we have learned about

### Chapter 4. Sequential Logic Circuits

Chapter 4 Sequential Logic Circuits 1 2 Chapter 4 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of