Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker


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1 Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker Note: + implies OR,. implies AND, ~ implies NOT Question 1: a) (4%) Use transmission gates to design a 3input OR gate Note: There are other solutions as well which use the same number of transistors.
2 b) (11%) Now use transmission gates to construct the following function: F = (A+B+C).(D+E) The maroon circle is A+B+C. This is fed to the top uncircled transmission gate with positive control input = D+E (yellow circle) and negative control input = ~(D+E) = ~D.~E (green circle). The 2 uncircled transmission gates form a 2input AND to realize Out = (A+B+C).(D+E)
3 Question 2: a) (11%) Use transmission gates to design a multiplexer with select signals S0, S1, inputs A, B, C, D, and output Out. You can arrange the signals in any way you want. One implementation is as follows: S1 S0 Out 0 0 A 0 1 B 1 0 C 1 1 D
4 b) (4%) Now suppose input A is always logic 0 and B is always logic 1. Can you make the circuit simpler? Only an NMOS is required to transmit a 1 and only a PMOS to transmit a 0. So we can eliminate a couple of transistors:
5 Question 3: Consider the function: X = A.B.C.D + E.F.G.H a) (4%) Draw its logic gate diagram using negative gates only (NAND, NOR, INV) b) (8%) Draw the stick diagram of each unique gate you have used above (i.e. if you have used 2 gates of the same type, just draw the stick diagram once) 4input NAND 2input NAND
6 c) (5%) Draw a compound gate transistor level diagram of X
7 Question 4: a) (4%) Suppose you have a design constraint that your gates can have a maximum of 2 inputs. Redraw the logic gate diagram of X using negative gates only. This is a tricky problem. Assuming complement signals like ~A are not available, this is the solution: But if complement signals are available, there is a slightly simpler solution:
8 b) (6%) Redraw the logic gate diagram of X using positive gates only (AND, OR) and the same constraint  gates can have a maximum of 2 inputs. Notice that a 4input AND gate can be directly decomposed into a cascade of two 2input AND gates followed by another AND gate. That s because it s a positive gate. The same cannot be done with negative gates.
9 Question 5: a) (3%) Show the truth table for a 2input XOR gate and give its logic equation: A XOR B =? A XOR B = A.~B + ~A.B A B A XOR B b) (10%) A 3bit parity checker counts the number of 1 s in a sequence of 3 bits and outputs 1 if odd, 0 if even. (Example: If the input is 101, output is 0, but if the input is 001, output is 1). Design this circuit using negative gates only and draw the transistor level diagram. You can assume that negative inputs like ~A are available. A B C Out The truth table outputs logic 1 in 4 cases. Combining these terms, we can write: Out = ~A.~B.C + ~A.B.~C + A.~B.~C + A.B.C In general, any XOR gate outputs logic 1 if the total number of input 1 s are odd, otherwise it outputs logic 0. So a 3bit parity checker is simply a 3input XOR gate: (A XOR B) XOR C = (A.~B + ~A.B).~C + ~(A.~B + ~A.B).C This eventually simplifies to the above expression for Out.
10 ~
11 Question 6: (10%) Consider the following 2to1 MUX built using transmission gates as shown in class. The ~pickx signal is generated from an inverter which has a delay of 2 time units. Look at the given timing diagram and draw the waveform for Out from beginning to end. Is there any period of time when Out isn t well defined? Due to the 2 unit inverter delay, both the transmission gates are ON during these time periods: 1012, 2022, For the first 2 cases, both inputs are the same and there is no conflict. For 3032, both pickx and ~pickx are logic 0, so both PMOS are conducting and there is a conflict between X and Y. You might expect X to win the conflict because PMOS can pass strong 1 s and weak 0 s. Actually we don t know what happens. Since the Out signal might be driving other parts of the circuit, we should never allow such a glitch or undefined state to occur.
12 Question 7: (20%) Design a latch with: Inputs = D, Clock, Set, Reset Output = ~Q Activehigh asynchronous Reset Activehigh synchronous Set This means that: Reset Clock Set ~Q 1 Don t care Don t care Load new ~D 0 0 Don t care Retain previous ~Q Notice the basic structure of the latch transmission gate followed by a loop consisting of 2 negative gates and a transmission gate. The NAND is added inside the loop to ensure Asynchronous Reset, while the OR outside the loop implements Synchronous Set. Note: Set sets output Q to 1, that s why ~Q is 0. Similarly Reset should make Q = 0, so ~Q = 1. Note: Generally positive gates like OR aren t recommended. It s better to replace them with negative logic depending on the technology/circuits used.
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