LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.


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1 Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. School of Mechanical Engineering Pusan National University
2 Digital IC packages TTL (transistortransistor logic) Highpower consumption, fast 74 series CMOS (complementary metaloxidesemiconductor) Lowpower consumption, slow Weak to static 4 series 74 Vcc 4B 4A 4Y 3B 3A Y A B Y 2A 2B 2Y GND DIP (dualinline) package Flattype Surfacemount package 2
3 3
4 Outline Combinational logic circuits Output depends on only the present inputs; not on the past inputs Multiplex ROM Decoder RAM PLD Sequential logic circuits Output depends on both the present and past inputs; hence having memory function Flipflops Counters 4
5 Combinational logic circuits (modules) Multiplex ROM Decoder RAM PLD 5
6 Calculator Input Output Decimal 4 bits Encoder CPU Decoder BCD 4 bits BCD 7 bits Key pad 7sement display 6
7 Half adder (HA) 2 inputs: and Y 3 outputs: S (sum, LSB) and C OUT (carry, MSB) C OUT Y S Y Y Y Y C OUT S Y HA S C OUT Y S C OUT 7
8 Full adder (FA) 3 inputs:, Y, and C 2 outputs: S and C OUT C Y Y C C OUT S FA S C OUT Y S YC C ( YC ( Y C YC YC Y C YC ) ( Y C Z Z Z OUT YC YC YC Y C Y C Y C Y ( C Y C YC YC ) ( YC ( ) C YC ( Y ) ) C ( Y ) YC ) YC YC YC [ ( Y Y ) Y ( )] ( Y Y ) ) YC YC ( Y Y ) Y ( C YC C YC HA HA Y S ) C Y C OUT 8
9 For the output S: YC S YC YC Y C YC YC Y C S For the output C OUT : YC C OUT C OUT Y C Y C Y C Y ( C Y C ( YC Y ) [ ( Y Y ) Y ( ) C ( Y ) ( Y Y ) )] 9
10 Multiplexers Selecting one of many inputs (also called data selectors) Consisting of 2 n data lines, n address lines, output, enable control input Ex) 4to MU
11 ROM Readonly memory Holding information in storage ( memory ) that cannot be altered but can be read by a logic circuit Consisting 2 m n cells m = # of address lines n = # of bits in each word stored in ROM When an address line is selected, the binary word corresponding to the address selected appears at the output c.f., EPROM (erasable programmable ROM) Ex) ROM
12 Ex) 8word 4bit (or 2 2 4) ROM A B C F F F 2 F 3 typical data stored in ROM (2 3 words of 4bits each) 2
13 Decoder Identifying, recognizing, and detecting a particular code N M decoder N inputs 2 N input codes Representing a binary number Activating only the output that corresponds to that input number M outputs Activated (HIGH) with only one of the M outputs for each input code LOW for the other outputs Ex) 3 8 decoder, 4 (BCDtodecimal) decoder, BCDto7 segment decoder N inputs 2 Decoder Y Y Y 2 M outputs N Y M 2 N input codes Only one output is HIGH for each input code 3
14 Ex) 2 4 decoder A B A B 2 4 decoder Y Y Y 2 Y 3 Y Y Y 2 Y 3 4
15 Ex) 3 8 decoder a b c y y y 2 y 3 y 4 y 5 y 6 y 7 5
16 Ex) BCDtodecimal decoder 74LS42, 74HC42 BCD Input Decimal Output A B C D activelow outputs 6
17 Decoder and RAM Commonly used for address decoding or memory expansion Ex) 2to4 decoder SRAM (static random access, or read and write, memory) 7
18 Encoder Opposite to the decoding process Only one of input lines is activated at a given time Producing an Nbit output code M inputs only one HIGH at a time 2 Encoder Y Y Y 2 Nbit output code M Y N 8
19 Ex) 8 3 decoder y y y 2 y 3 y 4 y 5 y 6 y 7 a b c d 9
20 Ex) DecimaltoBCD encoder +5 V Switch on 3: ABCD = Switch on 7: ABCD = A B C D 2
21 PLD Programmable logic device PROM (programmable readonly memory) PLA (programmable logic array) PAL/GAL (programmable array logic/generic array logic) Arrays of gates (e.g., AND and OR gates) having interconnections that can be programmed to perform a specific logical function Programming language: hardware description languages (HDLs) Used for various digital logic designs 2
22 Timing diagram 22
23 Sequential logic circuits Combinational logic circuits provide outputs that are based on a combination of present inputs only Sequential logic circuits depend on present and past input values (it memorizes!) Being able to store information 23
24 Flipflops Basic information storage device in a digital circuit Many different varieties of flipflops RS FF D FF JK FF T FF Common characteristics Bistable device Remaining in one of two stable states ( and ) until appropriate conditions cause FF to change state Memory element Two outputs; complement ( Q) and uncomplement (Q) outputs Synchronous operation by a clock signal Asynchronous operation Independent of the clock Level sensitive ( Latch ) 24
25 RS filpflop Two inputs (S set and R reset ), two outputs (Q and Q, called the state of FF) Requiring the FF to set and reset at the same time! Time delays! 25
26 R S Q 26
27 Ex) Initial state Q = (then, Q = ); apply S = Q = S Q = = SET Q becomes ; Q = = still SET Crosscoupled feedback from outputs Q and Q to the input of the NAND gates is such that the set condition sustains itself 27
28 RS FF with enable (E), preset (P), and clear (C) inputs R or S is effective only when E = Synchronizing signal Direct inputs P and C allow the user to preset or clear the FF at any time (asynchronous operation) S = (preset) when P = Q = (cleared) when C = 28
29 Delay latch (or delay element) An extension of RS FF Always R = S SET whenever E = Prohibiting R = S = ; eliminating R input Once E =, FF is latched to the previous value of the input ( memory ) and delays the output by one clock count w.r.t. the input E D Q No change 29
30 D flipflop An extension of data latch with two RS FFs Changing state only on the positive edge of the clock (leading or positive edgetriggered) Similarly, trailing or negative edgetriggered D FF D CLK Q D CLK Q indicating leading edgetrigger 3
31 Note that C implies the control signal D Q D C Q CLK D Q Q CLK Q Q D Q CLK Q Q 3
32 JK flipflop Same as RS FF except that J = K = states J Q CLK K Q J K Q No change Reset Set Toggle J Q CLK K Q J K CLK Q 32
33 indicating trailing edgetriggerc (no change) 33
34 J K Q 34
35 Master/slave FF Delayed output by the width of clock pulse Master Slave J K Q n+ J Q CLK K Q J Q CLK K Q Q n (no change) Reset Set Q n (toggle) CLK J t n master t n+ slave K Q 35
36 T flipflop JK FF with its inputs tied together 36
37 클럭이들어올때마다상태가바뀌는회로 출력신호가정확히 T 입력신호주파수의절반 + V CC Q D Q J Q T T CLK Q T CLK Q K Q D FF JK FF T Q EN J Q EN T CLK K Q Q 37
38 3bit binary up counter Force a RESET 38
39 Decade counter Count from to 9 and then RESET Impractical due to propagation delays 39
40 Ripple counter Consists of a cascade of 3 JK FFs 4
41 Rippleup counter Asynchronous counter T FF n serial cascades = (2 n ) counter Slow CLK Q (LSB) Q Q 2 Q Q T Q T Q 2 T 2 Q Q Q Q Q 2 Q T Q T Q 2 T 2 Q Q 4
42 Rippledown counter Asynchronous counter CLK Q (LSB) Q Q 2 Q Q T Q T Q 2 T 2 Q Q
43 Synchronous counter Parallel counter Fast Complex Q Q Q 2 Q 3 J Q J Q J 2 Q 2 J 3 Q 3 CLK CLK CLK CLK K K K 2 K 3 F F F 2 F 3 + V CC 43
44
45 Divider circuit 45
46 Synchronous counter 46
47 Ring counter 47
48 Parallel register The load input (clock) simultaneously transfers the parallel input binary word b 3 b 2 b b (store!) 48
49 Shift register 49
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