Novel Devices and Circuits for Computing

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Annabel Wright
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1 Novel Devices and Circuits for Computing UCSB 594BB Winter 2013 Lecture 4: Resistive switching: Logic

2 Class Outline Material Implication logic Stochastic computing Reconfigurable logic

3 Material Implication Logic: Main Idea Roff >> RG Ron << RG

4 Experimental Demonstration

5 NAND via implication

6 Implication Logic Pros Inherently nonvolatile (intermittent power supply) The finest grain pipeline (high throughput?) Complicated peripheral circuitry Cons: Switch device with every logic operation Power hungry (1 pj per operation) Feynman grand challenge New ideas for processing in memory

7 Similar to Mat Imp Concepts but relying on Multistate Let s do arithmetic operations by exploiting intermediate state, e.g. A = A + B A S = A is stored state tt B is coded to be proportional to pulse duration and/or pulse height Good or bad idea?

10 Can also do division, multiplication Base 512 was demonstrated

11 Stochastic Computing

12 Stochastic computing Original idea due to John von Neumann in 1953 Represent numbers [0,1] as stream of random bits and reconstruct numbers by calculating frequencies Pa = ¾, Pb = ½ Pa*Pb = 3/8

13 Stochastic computing: Cons and Pros PROS: Simple hardware for multiplication and addition Robust against noise Provide rough estimate quickly with precision increasing with time CONS: Exponential increase of operation (or HW) with precision For N bit binary multiplication (2N bit product) needs 2 2N samples to have equivalent precision and, e.g. 2 4N samples to have standard deviation of average frequency within the same precision Need random number generator

15 GOOD PROJECT/PAPER FOR RESEARCH!

16 Ideas for Memristor based Stochastic Computing?

17 Reconfigurable Logic

18 Island Type FPGA routing wires logic logic logic block block block flip clock logic block logic block logic block flop three state LUT buffers logic logic logic block block block memory bits Mux

19 Example of Mapping 4 bit Adder to 3 LUTs c 0 =0 full adder a abc in 0 s 0 b c in 0 c 1 full adder s 1 a 1 b 1 c 2 full adder a 2 s 2 b 2 c 3 full adder s 3 a 3 b 3 C 4 input output a b c in sum c out s c out a L 0 L 0 b c out 0 s Ripple carry adder Truth table Full adder circuit LUT implementation

20 Example of Mapping to FPGA c a 0 b 0 s b 0 b a 0 L 0 a 0 L c c s c a 1 b 1 s

21 Cons and Pros of FPGAs Circuitry is customized for a particular computation (massively parallel, bit granularity) Long configuration time good for repetitive or slowly changing computations Not as transparent for programmer and easy as up and Very high overhead for reconfigurability

216, 2007 21% 9% 5% Interconnect Clock IO

22 Dominant Area and Power Mingijie Lin, El Gamal, Simon Wong, IEEE Tran CAD, 26(2), pp. 216, % 9% 5% Interconnect Clock IO 65% CLB XC4003A data from Eric Kusse (UCB MS 1997)

23 Hybrid CMOS/Memristor FPGA: Main Idea typical FPGA and with lifted config. bits metallization config. bits & logic metallization & config. bits logic ~ 90% is interconnect (memory bits + three state buffers/pass gates) Crosspoint memristive device somewhere in the layer above CMOS Density, speed, power improvement configurable ASIC

24 Hybrid CMOS Memristor FPGA: First (a) (c) (d) Demo n anowire layer 2 (titanium) memristive layer NOT gate AND gate nanowire layer 1 (platinum) OR gate CMOS layer (b ) NOT gate NAND gate AND gate NAND gate NOR gate OR gate D flip flop Q. Xia et al. Nano Letters, 2009 NOR gate D flip flop 10x improvement in density (theoretical) as compared to pure CMOS with comparable power and latency

26 CMOL FPGA Use memristors not only as interconnect but also to implement part of functionality Analog properties of memristors to implement linear threshold gates Generic CMOL FPGA cell A+B B A B A B F nanodevices Linear Threshold Logic x 1 x 2 x 3 x 4 R ON V 0 CMOS D flip flop A R ON C wire R pass A+B CMOS inverter Memristors logic and routing N R L V OUTPUT L. Gao Trans. Nanotechnology 2013 Strukov and Likharev, Nanotechnology, 2005

27 Open Research Problems with Reconfigurable Logic 1) The lowerthe resistance the moreoverheadoverhead for CMOS programming circuitry what is the optimum? 2) Wh i h l i l f h i h 2) When switches are relatively free what is the new optimum architecture for switch box/interconnect/logic?

Choices for Interconnect Topology BUS vs

(++) hi (i everything (given enough time) can

sequentialize I/B Area (++) kn switches O(n)

) Bisection bandwidth n kn 2 switches O(n 2 )

28 Choices for Interconnect Topology BUS vs CROSSBAR Flexibility (+) routes Flexibility (++) hi (i everything (given enough time) can be tricky to schedule use optimally Delay (Power) ( ) wire length O(kn) parasitic stubs: kn+n series switch: 1 O(kn) sequentialize I/B Area (++) kn switches O(n) routes everything (guaranteed) Delay (Power) ( ) wire length O(kn) parasitic stubs: kn+n series switch: 1 O(kn) Area ( ) Bisection bandwidth n kn 2 switches O(n 2 )

29 Exploit Locality: Rent s Rule In the world of circuit design, an empirical relationship to capture: IO = c N p 0 p 1 p characterizes interconnect richness Typical: 05 p p 0.7 High Speed Logic p=0.67

30 Rent and Locality Rent and IO capture/quantifying locality local consumption local fanout

31 Exploit Locality Wires expensive Local interconnect cheap 1D versions What does this do to Switches? Delay?

32 Exploit Locality Wires expensive Local interconnect cheap Use 2D to make more things closer Mesh?

33 Mesh Analysis Flexibility? Ok w/ large w Delay (Power) Series switches 1 n Wire length w w n Stubs O(w) O(w n) O(w n) Assuming that BW scales as N P (from Rent Rule) w Area Bisection BW w n Switches O(nw) O(w 2 n) n blocks W N p N N p 0.5 For large N always wire limited!

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