Datapath Component Tradeoffs

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Chad Osborne
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1 Datapath Component Tradeoffs

2 Faster Adders Previously we studied the ripple-carry adder. This design isn t feasible for larger adders due to the ripple delay. ʽ There are several methods that we could exploit to create faster adders

3 Faster Adder Method 1: Two-level Logic Adder One way to generate a faster adder would be to apply two-level logic optimizations Will be very fast Circuit will be HUGE beyond 8 bits. This isn t really a feasible option

4 Faster Adder Method 2: Carry-Lookahead Adder Circuitry allows the higher bits to quickly determine if lower bits would generate a carry. Lets start by redesigning the Full Adder using Half Adders: Full Adder co = a b + b ci + a ci s = a b ci ʽ

5 Faster Adder Method 2: Full Adder Redesign A Half Adder is defined by the equations co = a b s = a b A Full Adder is defined by the following equations ɐ뱆擰 Ч co = a b + b ci + a ci = a b + b ci (a+a ) + a ci (b+b ) = a b + a b ci + a b ci + a b ci + a b ci = a b + a b ci + ci (a b + a b) = a b (1 + ci) + ci (a b) = a b + ci (a b) s = a b ci = (a b) ci Do you see the equations for a half adder in the full adder equations?

6 Faster Adder Method 2: Full Adder Redesign Schematic a i b i c i HA HA P i Gi s i c i+1

7 Faster Adder Method 2: Carry-Lookahead Logic Using this newly redesigned Adder, we can use the output of the first HA to provide useful carry-ahead information. ɐ썆擰 Ч Pi is called the Carry Propagate This is asserted only when a the carry-in propagates through this level. Gi is called Carry Generate This is asserted only when the addition of a & b will generate a carry.

8 Faster Adder Method 2: Carry-Lookahead Logic To determine how to create look ahead logic, lets examine the carries that would be generated by adding two 4-bit numbers, a & b: c1 = a0 b0 + (a0 b0) c0 = G0 + P0 c0 c2 = a1 b1 + (a1 b1) c1 = G1 + P1 c1 = G1 + P1 (G0 + P0 c0) = G1 + P1 G0 + P1 P0 c0 c3 = a2 b2 + (a2 b2) c2 = G2 + P2 c2 ʽ擰 Ч = G2 + P2 (G1 + P1 G0 + P1 P0 c0) = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 c0 c4 = a3 b3 + (a3 b3) c3 = G3 + P3 c3 = G3 + P3 (G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 c0) = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 c0

9 Faster Adder Method 2: Carry-Lookahead Adder Schematic The carry-propagate adder can now be redesigned: ɐ콆蔐 ь

10 Faster Adder Method 2: Iterative Carry-Lookahead Adder Carry-Lookahead has a problem The Fan-In of gates in the carry-lookahead logic increases as the number of bits increases. This can get unwieldy quickly. 4 or 8 bits is reasonable The answer is an iterative structure. Create smaller look-ahead adders Connect them together into a larger adders 退 Example: Create a 16-bit adder from 4 carrylookahead 4-bit adders in a ripple configuration. Is this a good enough design?

11 Faster Adder Method 2: Hierarchical Carry-Lookahead Adder Our initial optimization was aimed at removing ripple carries can we just apply the same optimization again? YES! ɐ蔐 ь Create a second layer of carry-lookahead for the iterative carry-lookahead adders. Creates a hierarchy of lookahead logic

12 Faster Adder Method 2: Hierarchical Carry-Lookahead Adder ʽ

13 Faster Adder Method 3: Carry-Select Adder Use multiple adders to compute all possible outcomes. Choose the correct outcome based off the carry generated by lower order adder. ɐ狰 ѡ Example: 8-bit carry-select adder using 4-bit adders

14 Faster Adder Tradeoff Comparison ʽ

15 Serial vs. Concurrent Optimizations & Tradeoffs Many tradeoffs and optimizations simplify to restructuring a design to take advantage of either: Serialization ɐ蔐 ь Performing tasks one at a time Leads to smaller designs, but is slower Concurrancy Performing tasks in parallel Fast, but larger designs

16 Pipelining Intuitive example: Washing dishes with a friend, you wash, friend dries You wash plate 1 Then friend dries plate 1, while you wash ʽ plate 2 Then friend dries plate 2, while you wash plate 3; and so on You don t sit and watch friend dry; you start on the next plate Pipelining: Break task into stages. Stages are processed sequentially Stages are evaluated concurrently Each stage works on a different piece of data. Result is assed to the next stage. Without pipelining: W1 D1 W2 D2 W3 D3 With pipelining: W1 W2 W3 D1 D2 D3 Time a Stage 1 Stage 2

17 Pipelining Example W X Y Z W X Y Z clk + + 2ns + 2ns 2ns Longest path is 2+2 = 4 ns So minimum clock period is 4ns ɐf 蔐 ь Stage 1 Stage 2 clk + + 2ns + 2ns 2ns Longest path is only 2 ns pipeline registers So minimum clock period is 2ns S clk S clk S = W+X+Y+Z S S(0) S(1) Datapath on left has critical path of 4 ns, so fastest clock period is 4 ns Can read new data, add, and write result to S, every 4 ns Datapath on right has critical path of only 2 ns So can read new data every 2 ns doubled performance (sort of...) S S(0) S(1)

18 Pipelining Example W X Y Z W X Y Z clk Longest path is 2+2 = 4 ns So mininum clock period is 4 ns clk Longest path is only 2 ns pipeline registers So mininum clock period is 2 ns S clk S clk S S(0) S(1) S S(0) S(1) (a) (b) Pipelining requires refined definition of performance Latency: Time for new data to result in new output data (seconds) Throughput: Rate at which new data can be input (items / second) So pipelining above system: Doubled the throughput, from 1 item / 4 ns, to 1 item / 2 ns Latency stayed the same: 4 ns

19 Concurrency Concurrency: Divide task into subparts, execute subparts simultaneously Dishwashing example: Divide stack into 3 substacks, give نsubstacksɐ to 3 neighbors, who work simultaneously 3 times speedup (ignoring time to move dishes to neighbors' homes) Concurrency does things side-byside; pipelining instead uses stages (like a factory line) Task Pipelining Concurrency Can do both, too

20 Component Allocation Another RTL tradeoff: Component allocation Choosing a particular set of functional units to implement a set of operations e.g., given two states, each with multiplication Can use 2 multipliers (*) OR, can instead use 1 multiplier, and 2 muxes Smaller size, but slightly longer delay due to the mux delay A B t1 := t2*t3 t4 := t5*t6 FSM-A: (t1ld=1) B: (t4ld=1) t2 t3 t5 t6 ʽ 㭆 A: (sl=0; sr=0; t1ld=1) B: (sl=1; sr=1; t4ld=1) sl t2 t5 2 1 t3 t6 2 1 sr size 2 mul 1 mul t1 (a) t4 t1 (b) t4 delay (c)

21 Operator Binding Another RTL tradeoff: Operator binding Mapping a set of operations to a particular component allocation Note: operator/operation mean behavior (multiplication, addition), while component (aka functional unit) means hardware (multiplier, adder) Different bindings may yield different size or delay A B C A B C t1 = t2 * t3 t4 = t5 * t6 t7 = t8 * t3 t1 = t2 ɐቆ * t3 t4 = t5 * t6 t7 = t8 * t3 t2 t3 t5 t8 t6 t3 sl 2x1 2x1 sr 2 muxes vs. 1 mux t2 t8 sl 2x1 t3 t5 t6 size Binding 1 Binding 2 2 multipliers allocated MULA MULB MULA MULB delay t1 t4 t7 t1 t7 Binding 1 Binding 2 t4

22 Operator Scheduling Yet another RTL tradeoff: Operator scheduling Introducing or merging states, and assigning operations to those states. A (some operations) B t1 = t2*t3 t4 = t5*t6 C (some operations) б A B B2 C (some operations) t1 = t2 * t3 t4 = t5 * t6 * t4 = t5 t6 (some operations) t2 * t1 t3 t5 * t4 t6 size a 3-state schedule 4-state schedule sl smaller (only 1 *) t2 t5 2x1 t1 * t3 t6 2x1 sr t4 but more delay due to muxes, and extra state delay 22

23 Optimization Level Typically, optimizations and tradeoffs made at higher design levels have a greater impact. i.e. Changes made during the RTL design will have much more effect Ш than optimizing a gate design. High level algorithm changes can have a major effect on the size and speed of the circuit. A classic example of algorithm selection is for search algorithms A binary search is much faster than a linear search. Lower level changes only serve to tune higher level changes.

24 Power Optimization & Tradeoffs Most power dissipation in a CMOS transistors occurs during switching. Known as dynamic power P = k * CV 2 f P Power k a constant for the transistor C Capacitance of the transistor V Voltage across the transistor f Switching frequency ʽ 但 Voltage and frequency are the two most easily modified parameters Voltage Voltage reduction is desirable due to the quadratic contribution to power. Low voltage gates can be smaller, which also reduces capacitance Low power gates generally have longer delays. Frequency Slower circuits switch less often and so burn less dynamic power This comes at the cost of performance.

25 Clock Gating Clock gating is a technique for disabling sections of a circuit by preventing the propagation of a clock signal. This is generally a bad idea as it can introduce skew. If you are interested in this topic, read the section on the book on p 甠 Ш

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building