Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.

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1 Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational Logic 1

2 Design Procedure 1. Determine the number of inputs and outputs 2. Assign symbols 3. Derive the truth table 4. Obtain simplified functions for each output 5. Draw the logic diagram ADDERS The most basic arithmetic operation os the addition of two binary digits. Combinational Logic 2

3 Design Procedure Half-Adder - Needs 2 inputs and 2 outputs. - x,y: inputs; S,C outputs. X Y C S Combinational Logic 3

4 Full Adder Consists of 3 inputs and two outputs: x,y: two significant bits z: carry x y z Use K maps for the two outputs Combinational Logic 4

5 Full Adder S = C = xy+xz+yz S = z (x y) C =m 3 + m 5 + m 6 + m 7 = Combinational Logic 5

6 Code Conversion Convert code A to B: BCD A? B Excess-3 code BCD Excess-3 (self complementing) A B C D w x y z Combinational Logic 6

7 A B C D w x y z Dr. Panos Nasiopoulos Combinational Logic 7

8 z = y = x = w = Combinational Logic 8

9 Analysis Procedure Dr. Panos Nasiopoulos Given: a logic diagram We want to derive the output Boolean function(s) Procedure: Combinational Logic 9

10 Analysis Procedure Dr. Panos Nasiopoulos T2 = ABC T1 = A+B+C F2 = AB + AC + BC T3 = F2 T1 F1 = T3 + T2 F1= Combinational Logic 10

11 Analysis Procedure TRUTH TABLE: Determine the number of input variables Label the outputs Obtain the truth table T2 = ABC T1 = A+B+C F2 = AB + AC + BC T3 = F2 T1 F1 = T3 + T2 A B C F2 F 2 T1 T2 T3 F Combinational Logic 11

12 Binary Parallel Adder Two binary numbers of n bits can be added by using FAs. The sum of two n bit binary numbers, A and B, can be generated in serial or in parallel. Serial: Combinational Logic 12

13 Binary Parallel Adder Parallel adder: Uses n FAs. Combinational Logic 13

14 Example: BCD to excess 3 code converter Dr. Panos Nasiopoulos Recall that we needed 11 gates for this design. 1 BCD input IC FA Excess-3 output Combinational Logic 14

15 Carry Propagation Recall that for the design of the parallel adder to work, the signal must propagate through the gates before the correct output sum is available. Total propagation time = propagation delay of a typical gate x the number of gates Let s look at S3. Inputs A3 and B3 are available immediately. However, C3 is available only after C2 is available. C2 has to wait for C1, etc. C4 The number of gate levels for the carry to propagate is found from the FA circuit 2 gates Combinational Logic 15

16 Combinational Logic 16

17 Carry lookahead: Pi = Gi = Si = Gi : called a carry generate; it produces a carry of 1 when both Ai and Bi are 1, regardless of the input carry Ci. Pi : called carry propagate because it is the term associated with the propagation of the carry from Ci to C i+ 1. C0 = input carry C1 = C2 = C3 = Combinational Logic 17

18 C0 = input carry C1 = C2 = C3 = Dr. Panos Nasiopoulos Combinational Logic 18

19 A 4-bit adder using a carry lookahead scheme: Dr. Panos Nasiopoulos Note that all output carries are generated after a delay of two levels of gates. S1 to S3 have equal propagation delay times Combinational Logic 19

20 Binary Subtractor Recall that the subtraction of two numbers (A-B) is done by taking 2 s complement of the ve number and then we add the 2 numbers. 2 s complement is 1 s complement + 1 B3 A3 B2 A2 B1 A1 B0 A0 We want to figure out how to complement the ve number (e.g., B). Combinational Logic 20

21 Overflow Two n-bit numbers added result in n+1 It may result in overflow Example (4-bits) Note that overflow occurs when So, if we want to detect the overflow, we can use Combinational Logic 21

22 Design of a BCD Adder Add two BCD numbers; show output in BCD format If we add two BCD numbers, the maximum output will be: carry (if 1) = 19 decimal. Using FAs, we get binary representation. We MUST convert it to BCD using two BCDs Combinational Logic 22

23 Design of a BCD Adder Dr. Panos Nasiopoulos Combinational Logic 23

24 Decoders A binary code of n bits can represent 2 n distinct combinations (or unique cases ). Decoder: a combinational circuit that converts n binary lines into 2 n unique output lines Example: a 3-to-8 line decoder 3 inputs are decoded to 8 outputs representing the 8 minterms Combinational Logic 24

25 Decoders Truth table for a decoder: Inputs Outputs x y z D0 D1 D2 D3 D4 D5 D6 D Decoder with NAND gates: Combinational Logic 25

26 Decoders Decoder with NAND gates and enable: Decoders with enable can be connected together to form larger decoders. Example: Design a 4-to-16 decoder Combinational Logic 26

27 Decoders: Implementing Boolean functions Dr. Panos Nasiopoulos Implement a FA using a decoder: Recall that the full adder has 3 inputs and two outputs: S(x,y,z) = Σ(1,2,4,7) C(x,y,z) = Σ(3,5,6,7) Combinational Logic 27

28 Encoders Inverse operation of a decoder It has 2 n inputs and generates n codewords Example: Design a 4 x 2 encoder E N C O D E R D0 D1 D2 D3 x y Problems: Combinational Logic 28

29 Design: Priority encoder Dr. Panos Nasiopoulos D0 D1 D2 D3 x y Combinational Logic 29

30 Multiplexers Dr. Panos Nasiopoulos A multiplexer selects one of many inputs and directs it to the output. ch1 ch2 Transmission line chn The selection may be controlled by select lines Normally 2 n lines: n select lines Example: 2 x 1 multiplexer x y MUX out How can we design this? Let s consider a 4 x 1 multiplexer MUX out Use code to direct input Combinational Logic 30

31 Multiplexers Dr. Panos Nasiopoulos Combinational Logic 31

32 Multiplexers used to implement Boolean functions Use a multiplexer to implement the following function: F = x y z + x yz + xy z + xyz z Z 1 z 0 Design a Full-adder S(x,y,z) = Σ(1,2,4,7); C(x,y,z) = Σ(1,2,4,7) x y z S Combinational Logic 32

Combina-onal Logic Chapter 4. Topics. Combina-on Circuit 10/13/10. EECE 256 Dr. Sidney Fels Steven Oldridge

Combina-onal Logic Chapter 4. Topics. Combina-on Circuit 10/13/10. EECE 256 Dr. Sidney Fels Steven Oldridge Combina-onal Logic Chapter 4 EECE 256 Dr. Sidney Fels Steven Oldridge Topics Combina-onal circuits Combina-onal analysis Design procedure simple combined to make complex adders, subtractors, converters