ECE 645: Lecture 2. Carry-Lookahead, Carry-Select, & Hybrid Adders

Transcription

1 ECE 645: Lecture 2 Carry-Lookahead, Carry-Select, & Hybrid Adders

2 Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 6, Carry-Lookahead Adders Sections Chapter 7, Variations in Fast Adders Section 7.3, Carry-Select Adders. Chapter 28, Reconfigurable Arithmetic Section 28.2, Adder Designs for FPGAs.

3 Carry-Lookahead Adders

4 Basic Signals Generate signal: Propagate signal: Anihilate (absorb) signal: Transfer signal: c out =1 given c in = 1 g i = x i y i p i = x i y i a i = x i y i = x i + y i t i = g i + p i = a i = x i + y i Carry recurrence c i+1 = g i + c i p i = g i + c i t i

5 Unrolling Carry Recurrence c i = g i-1 + c i-1 p i-1 = = g i-1 + (g i-2 + c i-2 p i-2 )p i-1 = g i-1 + g i-2 p i-1 + c i-2 p i-2 p i-1 = = g i-1 + g i-2 p i-1 + (g i-3 + c i-3 p i-3 )p i-2 p i-1 = = g i-1 + g i-2 p i-1 + g i-3 p i-2 p i-1 + c i-3 p i-3 p i-2 p i-1 = =.. = = g i-1 + g i-2 p i-1 + g i-3 p i-2 p i-1 + g i-4 p i-3 p i-2 p i g 0 p 1 p 2 p i-2 p i-1 + c 0 p 0 p 1 p 2 p i-2 p i-1 = i-2 i-1 i-1 = g i-1 + g k p j + c 0 p j k=0 j=k+1 j=0

6 4-bit Carry-Lookahead Adder (1) c 4 = g 3 + g 2 p 3 + g 1 p 2 p 3 + g 0 p 1 p 2 p 3 + c 0 p 0 p 1 p 2 p 3 c 3 = g 2 + g 1 p 2 + g 0 p 1 p 2 + c 0 p 0 p 1 p 2 c 2 = g 1 + g 0 p 1 + c 0 p 0 p 1 c 1 = g 0 + c 0 p 0 s 0 = x 0 y 0 c 0 = p 0 c 0 s 1 = p 1 c 1 s 2 = p 2 c 2 s 3 = p 3 c 3

7 4-bit Carry-Lookahead Adder (2) c 4 = g 3 + c 3 p 3 3 gates less c 3 = g 2 + g 1 p 2 + g 0 p 1 p 2 + c 0 p 0 p 1 p 2 c 2 = g 1 + g 0 p 1 + c 0 p 0 p 1 c 1 = g 0 + c 0 p 0 s 0 = x 0 y 0 c 0 = p 0 c 0 s 1 = p 1 c 1 s 2 = p 2 c 2 s 3 = p 3 c 3

8 4-bit Carry Network with Full Lookahead

9 4-bit Lookahead Carry Generator Equations c i+3 = g i+2 + g i+1 p i+2 + g i p i+1 p i+2 + c i p i p i+1 p i+2 c i+2 = g i+1 + g i p i+1 + c i p i p i+1 c i+1 = g i + c i p i g [i..i+3] = g i+3 + g i+2 p i+3 + g i+1 p i+2 p i+3 + g i p i+1 p i+2 p i+3 p [i..i+3] = p i p i+1 p i+2 p i+3

10 4-bit Lookahead Carry Generator Schematic

11 4-bit Lookahead Carry Generator Symbol

12 16-bit 2-level Carry Lookahead Adder c 15 c 14 c 13 c 11 c 10 c 9 c 7 c 6 c 5 c 3 c 2 c 1 g 14 p 14 g 12 p 12 g 15 p 15 g 13 p 13 g 10 p 10 g 11 p 11 g 9 p 9 g 8 p 8 g 7 p 7 g 6 p 6 g 4 p g 4 5 p 5 g 2 p 2 g 3 p 3 g 1 p 1 g 0 p 0 CLA GEN c 12 CLA GEN c 8 CLA GEN c 4 CLA GEN c 0 g [12,15] P [12,15] g [8,11] p [8,11] g [4,7] p [4,7] g [0,3] p [0,3] CLA GEN g [0,15] p [0,15]

13 Operation of the 16-bit 2-level Carry Lookahead Adder (1) Signals computed Formulas Delay g i, p i i=0..15 g i = x i y i p i = x i y i 1 gate delay g [i..i+3], p [i..i+3] i=0, 4, 8, 12 2 gate delays g [i..i+3] = g i+3 + g i+2 p i+3 + g i+1 p i+2 p i+3 + g i p i+1 p i+2 p i+3 p [i..i+3] = p i p i+1 p i+2 p i+3

14 Operation of the 16-bit 2-level Carry Lookahead Adder (2) Signals computed c 4, c 8, c 12 g [0..15], p [0..15] Formulas Delay 2 gate delays c 4 = g [0..3] + c 0 p [0..3] c 8 = g [4..7] + g [0..3] p [4..7] + c 0 p [0..3] p [4..7] c 12 = g [8..11] + g [4..7] p [8..11] + g [0..3] p [4..7] p [8..11] + c 0 p [0..3] p [4..7] p [8..11] g [0..15] = g [12..15] + g [8..11] p [12..15] + g [4..7] p [8..11] p [12..15] + g [0..3] p [4..7] p [8..11] p [12..15] p [0..15] = p [0..3] p [4..7] p [8..11] p [12..15]

15 Operation of the 16-bit 2-level Carry Lookahead Adder (3) Signals computed c i+1, c i+2, c i+3 i = 4, 8, 12 Formulas Delay 2 gate delays i.e., c 5, c 6, c 7, c 9, c 10, c 11, c 13, c 14, c 15 c i+3 = g i+2 + g i+1 p i+2 + g i p i+1 p i+2 + c i p i p i+1 p i+2 c i+2 = g i+1 + g i p i+1 + c i p i p i+1 c i+1 = g i + c i p i

16 Operation of the 16-bit 2-level Carry Lookahead Adder (4) Signals computed s i+1, s i+2, s i+3 i = 4, 8, 12 Formulas Delay 1 gate delay i.e., s 5, s 6, s 7, s 9, s 10, s 11, s 13, s 14, s 15 s i = p i c i Total: 8 gate levels in the CLA adder vs. 32 gate levels in the ripple carry adder

17 64-bit 3-level Carry Lookahead Adder c 31 c 30 c 29 c 27 c 26 c 25 c 23 c 22 c 21 c 19 c 18 c 17 c 48 c 32 c 28 c 24 c 20 CLA GEN CLA GEN CLA GEN CLA GEN c 16 c 0 g [28,31] p [28,31] g [24,27] p[24,27] g [20,23] p[20,23] g [16,19] p [16,19] CLA GEN g [48,63] p [48,63] g [32,47] p [32,47] g [16,31] p [16,31] g [0,15] p [0,15] CLA GEN g [0,63] p [0,63]

18 Level PRE 1 Operation of the 64-bit 3-level Carry Lookahead Adder g i, p i Signals computed i=0..63 Delay 1 gate delay g [i..i+3], p [i..i+3] i=0, 4, 8, 12,, 56, 60 2 gate delays 2 g [i..i+15], p [i..i+15] i=0, 16, 32, 48 2 gate delays 3 g [0..63], p [0..63] c 16, c 32, c 48, 2 gate delays 2 c 20, c 24, c 28, c 36, c 40, c 44, c 52, c 56, c 60 2 gate delays 1 c 21, c 22, c 23, c 25, c 26, c 27,, c 61, c 62, c 63 2 gate delays POST s 21, s 22, s 23, s 25, s 26, s 27,, s 61, s 62, s 63 1 gate delay

19 Delay of a k-bit Carry-Lookahead Adder T lookahead-adder = 4 log 4 k k T lookahead-adder T ripple-carry-adder

20 Carry-Select Adders

21 One-level k-bit Carry-Select Adder

22 One-level k-bit Carry-Select Adder Cost & Latency Units: cost and delay of a single 2-to-1 multiplexer

23 Two-level k-bit Carry Select Adder

24 Possible Design of a Carry-Select Adder on an FPGA 6 bits 4 bits 3 bits 2 bits 1 bit / 6 / 4 / 3 / 2

25 Hybrid Adders

26 A Hybrid Ripple-Carry/Carry-Lookahead Adder

27 A Hybrid Carry-Lookahead/Carry-Select Adder