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1 Slides for Lecture 19 ENEL 353: Digital Circuits Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 23 October, 2013
2 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 2/15 Previous Lecture Completion of material on K-maps with 5 or 6 input bits. Using K-maps for problems with multiple output bits. Introduction to multiplexers.
3 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 3/15 Today s Lecture 4:1 multiplexer implementations. Using multiplexers to implement combinational logic functions. Decoders and applications of decoders. Related reading in Harris & Harris: Sections and
4 Let s continue to make notes on these three designs for 4:1 mux circuits. S 1 S 0 S 1 S 0 D 0 D 0 D 1 S 1 S 0 S 0 S 1 D 2 D 3 D 1 D 2 S 1 S 0 S 1 S 0 Y D 0 D 1 D Y (a) Y D 3 (b) D 3 (c) 1 Image is Figure 2.58 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.
5 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 5/15 Base two logarithms: What does log 2 N mean? Base two logarithms are often useful in discussion of digital systems (and also in discussion of computing algorithms and data structures). You should already be familiar with natural (base e) and common logarithms, defined as follows: If y = e x, then x = ln y. If y = 10 x, then x = log 10 y. The definition for the base two logarithm works the same way: If y = 2 x, then x = log 2 y.
6 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 6/15 Wider multiplexers If you understand 2:1 and 4:1 muxes, it s very easier to generalize to N:1, if N is a power of two. The table to the right describes an 8:1 mux. How many select bits would be needed for a 16:1 mux? For a 32:1 mux? What would be a general formula for the number of select bits needed for an N:1 mux? S 2 S 1 S o Y D D D D D D D D 7
7 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 7/15 Using muxes to implement logic functions Multiplexers have a lot of practical applications. We ll see some of them later in this course or in ENCM 369 in Winter. For now, we ll just look at one such application: Given a truth table with N rows for a function F, it s very straightforward to make a circuit for F with an N:1 multiplexer as the key component.
8 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 8/15 Textbook graphical notation for HIGH and LOW voltage connections This schematic is an example of the symbols Harris & Harris use... connection to V DD (power supply) connection to ground What is the output of the AND gate? (This is supposed to be an easy question.)
9 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 9/15 Example of using muxes to implement logic functions How can we implement the given function with an 8:1 mux? How can we implement the given function with a 4:1 mux and an inverter? A B C Y
10 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 10/15 N:1 multiplexers with N not a power of two Sometimes a circuit requires selection of one of N signals, where N is not a power of two. This is easy to accommodate. For example, let s describe a 3:1 mux. Let s build a 3:1 mux from two 2:1 muxes. Let s build a 3:1 mux using a 4:1 mux.
11 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 11/15 Decoders A decoder has N inputs and 2 N outputs. Here are examples of 2:4 and 3:8 decoders... Y 7 Y 6 A 1 Y 3 2:4 Y 2 A 3:8 1 A 0 decoder decoder Y 1 Y 0 A 2 A 0 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 Let s write a description of the 2:4 decoder, then show how to make one using inverters and AND gates.
12 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 12/15 Building logic functions with decoders Because decoders are minterm generators, decoders can be used to go from truth tables to circuits in a very straightforward way. Let s illustrate this by making a 1-bit full adder out of a 3:8 decoder and some OR gates.
13 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 13/15 Decoders with enable inputs (This topic is not covered in Section 2.8 in the textbook.) A common variation of the decoder is a decoder with an enable input: A 1 A 0 2:4 decoder EN Y 3 Y 2 Y 1 Y 0 This is just like the 2:4 decoder we looked at earlier, except that when EN = 0, all outputs are 0. Let s write a truth table for this.
14 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 14/15 Using small decoders with enable inputs to make bigger decoders Let s build a 3:8 decoder using an inverter and two 2:4 decoder-with-enable circuits. Let s build a 4:16 decoder-with-enable using some 2:4 decoder-with-enable circuits.
15 ENEL 353 F13 Section 02 Slides for Lecture 19 slide 15/15 Upcoming topics Timing of combinational logic. Related reading in Harris & Harris: Section 2.9. Careful reading of this section is highly recommended!
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