Fundamentals of Computer Systems

Transcription

1 Fundamentals of omputer Systems ombinational Logic Stephen. Edwards olumbia University Fall 2012

2 Encoders and Decoders

3 Decoders Input: n-bit binary number Output: 1-of-2 n one-hot code 2-to-4 in out

4 Decoders Input: n-bit binary number Output: 1-of-2 n one-hot code 2-to-4 in out to-8 decoder in out

5 Decoders Input: n-bit binary number Output: 1-of-2 n one-hot code 2-to-4 in out to-8 decoder in out in 4-to-16 decoder out

6 The to-8 Decoder 15 Y Y1 Select Inputs 2 13 Y Y3 Y4 Data Outputs 10 Y5 G1 6 9 Y6 Enable Inputs G2 4 7 Y7 G2 5

7 138 Spotted in the Wild Pac-Man (Midway, 1980)

8 General n-bit Decoders Every minterm I n I 2 I 1 I n. I 2 I 1 I n I 2 I 1. I n I 2 I 1 I n I 2 I 1 I n I 2 I 1 I n I 2 I 1

9 General n-bit Decoders Every minterm I n I 2 I 1 Implementing a function with a decoder: E.g., F = + I n. I 2 I 1 I n I 2 I 1. I n I 2 I 1 I n I 2 I 1 I n I 2 I 1 I n I 2 I 1 F F

10 The Priority Encoder Input: 1-of-2 n Output: n-bit binary number for highest priority input EO GS 0 Inputs Outputs 3 13 E G E 1 XXXXXXXX XXXXXXX XXXXXX XXXXX XXXX XXX XX X EI

11 148 Spotted in the Wild Users would connect wires to interrupt sources; pull-ups quiet unconnected interrupts O68K1 Single-board omputer (Omnibyte 1983)

12 Multiplexers

13 The Two-Input Multiplexer 1 0 S Y S Y

14 The Two-Input Multiplexer 1 0 S Y S Y S S Y S Y 0 X X X X 1 S Y 0 1

15 The Four-Input Mux D Y D S 1 S 2 Y S 2 S 1 Y D S 2 S 1

16 Two-input Muxes in the Wild Quad 2-to-1 mux 3 selects color from a sprite or the background Pac-Man (Midway, 1980)

17 General 2 n -input muxes I 2 n 1. I 1 1 I n 1 S n S 2 S 1 Y I 2 n 1. I 1 Y Y = I 0 S n S 2 S 1 + I 1 S n S 2 S 1 + I 2 S n S 2 S 1 +. I 2 n 2S n S 2 S 1 + I 2 n 1S n S 2 S 1 I 0 2 n n-to-2 n decoder S n S 2 S 1

18 Using a Mux to Implement an rbitrary Function F = + F

19 Using a Mux to Implement an rbitrary Function F = + pply each value in the truth table: F F

20 Using a Mux to Implement an rbitrary Function F = + pply each value in the truth table: F F

21 Using a Mux to Implement an rbitrary Function F = + pply each value in the truth table: F F

22 Using a Mux to Implement an rbitrary Function F = + F

23 Using a Mux to Implement an rbitrary Function F = + F

24 Using a Mux to Implement an rbitrary Function F = + an always remove a select and feed in 0, 1, S, or S. F F Y

25 Using a Mux to Implement an rbitrary Function F = + an always remove a select and feed in 0, 1, S, or S. F F Y

26 Using a Mux to Implement an rbitrary Function F = + an always remove a select and feed in 0, 1, S, or S. F F Y

27 Using a Mux to Implement an rbitrary Function F = + an always remove a select and feed in 0, 1, S, or S. F F Y

28 Using a Mux to Implement an rbitrary Function F = + an always remove a select and feed in 0, 1, S, or S. F F Y In this case, the function just happens to be a mux: (not always the case!) 1 0 Y

29 Timing

30 omputation lways Takes Time 74LS00 lways a delay between inputs and outputs. auses: Limited currents charging capacitance The speed of light

31 The Simplest Timing Model In Out t p Each gate has its own propagation delay t p. When an input changes, any changing outputs do so after t p. Wire delay is zero.

32 More Realistic Timing Model In Out t p(max) t p(min) It is difficult to manufacture two gates with the same delay; better to treat delay as a range. Each gate has a minimum and maximum propagation delay t p(min) and t p(max). Outputs may start changing after t p(min) and stablize no later than t p(min).

33 ritical Paths and Short Paths D Y How slow can this be?

34 ritical Paths and Short Paths D Y How slow can this be? The critical path has the longest possible delay. t p(max) = t p(max, ND) + t p(max, OR) + t p(max, ND)

35 ritical Paths and Short Paths D Y How fast can this be? The shortest path has the least possible delay. t p(min) = t p(min, ND)

36 Glitches glitch is when a single input change can cause multiple output changes

37 Glitches glitch is when a single input change can cause multiple output changes

38 Glitches glitch is when a single input change can cause multiple output changes

39 Glitches glitch is when a single input change can cause multiple output changes

40 Glitches glitch is when a single input change can cause multiple output changes

41 Glitches glitch is when a single input change can cause multiple output changes dding such redundancy only works for single input changes; glitches may be unavoidable when multiple inputs change.

42 rithmetic ircuits

43 rithmetic: ddition dding two one-bit numbers: and Produces a two-bit result: S (carry and sum) Half dder S S

44 Full dder In general, you need to add three bits: o = = = = = = 10 i o S i i o S S

45 Four-it Ripple-arry dder o F i F F F F 0 S S 4 S 3 S 2 S 1 S 0

46 Two s omplement dder/subtractor To subtract from, add and. Neat trick: carry in takes care of the +1 operation SUTRT/DD F F F F S 4 S 3 S 2 S 1 S 0

47 Overflow in Two s-omplement Representation When is the result too positive or too negative?

48 Overflow in Two s-omplement Representation When is the result too positive or too negative? % % The result does not fit when the top two carry bits differ. n n n 1n S n S n % Overflow

49 Ripple-arry dders are Slow S3 S2 S1 S0 The depth of a circuit is the number of gates on a critical path. This four-bit adder has a depth of 8. n-bit ripple-carry adders have a depth of 2n.

50 arry Generate and Propagate The carry chain is the slow part of an adder; carry-lookahead adders reduce its depth using the following trick: K-map for the carry-out function of a full adder For bit i, i+1 = i i + i i + i i = i i + i ( i + i ) = G i + i P i Generate G i = i i sets carry-out regardless of carry-in. Propagate P i = i + i copies carry-in to carry-out.

51 arry Lookahead dder Expand the carry functions into sum-of-products form: i+1 = G i + i P i 1 = G P 0 2 = G P 1 = G 1 + (G P 0 )P 1 = G 1 + G 0 P P 0 P 1 3 = G P 2 = G 2 + (G 1 + G 0 P P 0 P 1 )P 2 = G 2 + G 1 P 2 + G 0 P 1 P P 0 P 1 P 2 4 = G P 3 = G 3 + (G 2 + G 1 P 2 + G 0 P 1 P P 0 P 1 P 2 )P 3 = G 3 + G 2 P 3 + G 1 P 2 P 3 + G 0 P 1 P 2 P P 0 P 1 P 2 P 3

52 The inary arry-lookahead dder Σ4 arry out i has i + 1 product terms, largest of which has i + 1 literals Σ3 If wide gates don t slow down, delay is independent of number of bits Σ2 Σ1 More realistic: if limited to two-input gates, depth is O(log 2 n). 7 0