Lecture 11: Adders. Slides courtesy of Deming Chen. Slides based on the initial set from David Harris. 4th Ed.
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1 Lecture : dders Slides courtesy of Deming hen Slides based on the initial set from David Harris MOS VLSI Design
2 Outline Single-bit ddition arry-ripple dder arry-skip dder arry-lookahead dder arry-select dder arry-increment dder Tree dder Readings:
3 Single-it ddition Half dder S out out S Full dder S out (,, ) S out S out S MJ out
4 PGK For a full adder, define what happens to carries (in terms of and ) Generate: out = independent of G = Propagate: out = P = Kill: out = 0 independent of K = ~ ~ 4
5 MJ Full dder Design I rute force implementation from eqns S out MJ (,, ) S out S out 5
6 Full dder Design II Factor S in terms of out S = + ( + + )(~ out ) ritical path is usually to out in ripple adder MINORITY out S S out 6
7 Layout lever layout circumvents usual line of diffusion Use wide transistors on critical path Eliminate output inverters 7
8 Full dder Design III omplementary Pass Transistor Logic (PL) Slightly faster, but more area S out S out 8
9 arry Propagate dders N-bit adder called P Each sum bit depends on all previous carries How do we compute all these carries quickly? N... N... out in S N... out in out in carries S
10 arry-ripple dder Simplest design: cascade full adders ritical path goes from in to out Design full adder to have fast carry delay out in 3 2 S 4 S 3 S 2 S 0
11 Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j G G P G i: j i: k i: k k : j P P P i: j i: k k : j 0:00:00inGP ase case G G Sum: i: i i i i P P i: i i i i Si Pi Gi :0 G0:0 G0 in P0:0 P0 0
12 PG Logic in G 4 P 4 G 3 P 3 G 2 P 2 G P G 0 P 0 : itwise PG logic 2: Group PG logic G 3:0 G 2:0 G :0 G 0: : Sum logic 4 out S 4 S 3 S 2 S 2
13 arry-ripple Revisited G G P G i:0 i i i : in G 4 P 4 G 3 P 3 G 2 P 2 G P G 0 P 0 G 3:0 G 2:0 G :0 G 0: out S 4 S 3 S 2 S 3
14 Delay arry-ripple PG Diagram it Position t t ( N ) t t ripple pg O xor 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 4
15 PG Diagram Notation lack cell Gray cell uffer i:k k-:j i:k k-:j i:j i:j i:j i:j G i:k P i:k G k-:j G i:j G i:k P i:k G i:j G k-:j G i:j G i:j P k-:j P i:j P i:j P i:j 5
16 arry-skip dder arry-ripple is slow through all N stages arry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal 6:3 6:3 2:9 2:9 8:5 8:5 4: 4: P 6:3 P 2:9 P 8:5 P 4: out in S 6:3 S 2:9 S 8:5 S 4: 6
17 arry-skip PG Diagram :0 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 For k n-bit groups (N = nk) tskip tpg 2 n ( k ) t O t xor 7
18 Variable Group Size :0 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 Delay grows as O(sqrt(N)) 8
19 arry-lookahead dder arry-lookahead adder computes G i:0 for many bits in parallel. Uses higher-valency cells with more than two inputs. 6:3 6:3 2:9 2:9 8:5 8:5 4: 4: out G 6:3 P 6:3 2 G 2:9 P 2:9 8 G 8:5 P 8:5 4 G 4: P 4: in S 6:3 S 2:9 S 8:5 S 4: 9
20 0 0 0 arry-select dder Trick for critical paths dependent on late input X Precompute two possible outputs for X = 0, Select proper output when X arrives arry-select adder precomputes n-bit sums For both possible carries into n-bit group 6:3 6:3 2:9 2:9 8:5 8:5 4: 4: out in S 6:3 S 2:9 S 8:5 S 4: 20
21 Tree dder If lookahead is good, lookahead across lookahead! Recursive lookahead gives O(log N) delay Many variations on tree adders 2
22 rent-kung :4 3:2 :0 9:8 7:6 5:4 3:2 :0 5:2 :8 7:4 3:0 5:8 7:0 :0 3:0 9:0 5:0 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 22
23 Sklansky :4 3:2 :0 9:8 7:6 5:4 3:2 :0 5:2 4:2 :8 0:8 7:4 6:4 3:0 2:0 5:8 4:8 3:8 2:8 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 23
24 Kogge-Stone :4 4:3 3:2 2: :0 0:9 9:8 8:7 7:6 6:5 5:4 4:3 3:2 2: :0 5:2 4: 3:0 2:9 :8 0:7 9:6 8:5 7:4 6:3 5:2 4: 3:0 2:0 5:8 4:7 3:6 2:5 :4 0:3 9:2 8: 7:0 6:0 5:0 4:0 5:0 4:0 3:0 2:0 :0 0:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 :0 0:0 24
25 Tree dder Taxonomy Ideal N-bit tree adder would have L = log N logic levels Fanout never exceeding 2 No more than one wiring track between levels Describe adder with 3-D taxonomy (l, f, t) Logic levels: L + l Fanout: 2 f + Wiring tracks: 2 t Known tree adders sit on plane defined by l + f + t = L- 25
26 Summary dder architectures offer area / power / delay tradeoffs. hoose the best one for your application. rchitecture lassification Logic Levels Max Fanout Tracks arry-ripple N- N ells arry-skip n=4 N/ N arry-inc. n=4 N/ N rent-kung (L-, 0, 0) 2log 2 N 2 2N Sklansky (0, L-, 0) log 2 N N/ Nlog 2 N Kogge-Stone (0, 0, L-) log 2 N 2 N/2 Nlog 2 N 26
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