CPE/EE 427, CPE 527 VLSI Design I L07: CMOS Logic Gates, Pass Transistor Logic. Review: CMOS Circuit Styles


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1 PE/EE 427, PE 527 VLI esign I L07: MO Logic Gates, Pass Transistor Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( ) Review: MO ircuit tyles tatic complementary MO  except during switching, output connected to either V or via a lowresistance path high noise margins full rail to rail swing VOH and VOL are at V and, respectively low output impedance, high input impedance no steady state path between V and (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) ynamic MO  relies on temporary storage of signal values on the capacitance of highimpedance circuit nodes simpler, faster gates increased sensitivity to noise 9/17/2005 VLI esign I;. Milenkovic 2 VLI esign I;. Milenkovic 1
2 Review: tatic omplementary MO Pullup network (PUN) and pulldown network (PN) In 1 In 2 In N In 1 In 2 In N PUN PN PMO transistors only pullup: make a connection from to F when F(In 1,In 2, In N ) = 1 F(In 1,In 2, In N ) pulldown: make a connection from F to when F(In 1,In 2, In N ) = 0 NMO transistors only PUN and PN are dual logic networks 9/17/2005 VLI esign I;. Milenkovic 3 OI221 Vdd E E Z 9/17/2005 VLI esign I;. Milenkovic 4 VLI esign I;. Milenkovic 2
3 tandard ell Layout Methodology Routing channel signals What logic function is this? 9/17/2005 VLI esign I;. Milenkovic 5 OI21 Logic Graph j PUN =!( ( + )) i i j PN 9/17/2005 VLI esign I;. Milenkovic 6 VLI esign I;. Milenkovic 3
4 Two tick Layouts of!( ( + )) uninterrupted diffusion strip 9/17/2005 VLI esign I;. Milenkovic 7 onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. i j For a single poly strip for every input signal, the Euler paths in the PUN and PN must be consistent (the same) 9/17/2005 VLI esign I;. Milenkovic 8 VLI esign I;. Milenkovic 4
5 onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. i j For a single poly strip for every input signal, the Euler paths in the PUN and PN must be consistent (the same) 9/17/2005 VLI esign I;. Milenkovic 9 OI22 Logic Graph PUN =!((+) (+)) PN 9/17/2005 VLI esign I;. Milenkovic 10 VLI esign I;. Milenkovic 5
6 OI22 Layout ome functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) 9/17/2005 VLI esign I;. Milenkovic 11 ombinational Logic ells (cont d) The OI family of cells with 3 index numbers or less = {OI, OI, O, O}; a,b,c={2,3} ell Type a1 a11 ab ab1 abc Total ells 21, , , 33, , 321, , 333, 332, 322 Number of Unique ells /17/2005 VLI esign I;. Milenkovic 12 VLI esign I;. Milenkovic 6
7 VT is ataependent M 3 M µ/0.25µ NMO 0.75µ /0.25µ PMO V G2 = V V 1 V G1 = V M 2 M 1 F= int 9/17/2005 VLI esign I;. Milenkovic weaker PUN 0 1 2,: 0 > 1 =1, :0 > 1 =1, :0>1 The threshold voltage of M 2 is higher than M 1 due to the body effect (γ) V Tn1 = V Tn0 V Tn2 = V Tn0 + γ( ( 2φ F + V int )  2φ F ) since V of M 2 is not zero (when V = 0) due to the presence of int tatic MO Full dder ircuit in in! out!um in in in 9/17/2005 VLI esign I;. Milenkovic 14 VLI esign I;. Milenkovic 7
8 tatic MO Full dder ircuit! out =! in & (!!) (! &!)!um = out & (!!! in ) (! &! &! in ) in in! out!um in in in out = in & ( ) ( & ) um =! out & ( in ) ( & & in ) 9/17/2005 VLI esign I;. Milenkovic 15 Pass Transistor Logic VLI esign I;. Milenkovic 8
9 NMO Transistors in eries/parallel Primary inputs drive both gate and source/drain terminals NMO switch closes when the gate input is high Y = Y if and Y = Y if or Remember NMO transistors pass a strong 0 but a weak 1 9/17/2005 VLI esign I;. Milenkovic 17 PMO Transistors in eries/parallel Primary inputs drive both gate and source/drain terminals PMO switch closes when the gate input is low Y = Y if and = + Y = Y if or = Remember PMO transistors pass a strong 1 but a weak 0 9/17/2005 VLI esign I;. Milenkovic 18 VLI esign I;. Milenkovic 9
10 Pass Transistor (PT) Logic 0 F = 0 F = Gate is static a lowimpedance path exists to both supply rails under all circumstances N transistors instead of 2N No static power consumption Ratioless idirectional (versus undirectional) 9/17/2005 VLI esign I;. Milenkovic 19 VT of PT N Gate 1.5/ / / /0.25 F= V out, V 1 0 =, = V in, V =, =0 ==0 Pure PT logic is not regenerative  the signal gradually degrades after passing through a number of PTs (can fix with static MO inverter insertion) 9/17/2005 VLI esign I;. Milenkovic 20 VLI esign I;. Milenkovic 10
11 ifferential PT Logic (PL) PT Network F F Inverse PT Network F F F= F=+ F= N/NN F= OR/NOR F=+ OR/NOR F= 9/17/2005 VLI esign I;. Milenkovic 21 PL Properties ifferential so complementary data inputs and outputs are always available (so don t need extra inverters) till static, since the output defining nodes are always tied to or through a low resistance path esign is modular; all gates use the same topology, only the inputs are permuted. imple OR makes it attractive for structures like adders Fast (assuming number of transistors in series is small) dditional routing overhead for complementary signals till have static power dissipation problems 9/17/2005 VLI esign I;. Milenkovic 22 VLI esign I;. Milenkovic 11
12 PL Full dder in in!um um in in in in! out out 9/17/2005 VLI esign I;. Milenkovic 23 PL Full dder in in!um um in in in in! out out 9/17/2005 VLI esign I;. Milenkovic 24 VLI esign I;. Milenkovic 12
13 NMO Only PT riving an Inverter In = V x = V G = V V V Tn M 1 M 2 V x does not pull up to, but V Tn Threshold voltage drop causes static power consumption (M 2 may be weakly conducting forming a path from to ) Notice V Tn increases of pass transistor due to body effect (V ) 9/17/2005 VLI esign I;. Milenkovic 25 Voltage wing of PT riving an Inverter In = 0 0.5/0.25 x 1.5/ /0.25 Out Voltage, V Out In x = 1.8V Time, ns ody effect large V at x  when pulling high ( is tied to and charged up close to ) o the voltage drop is even worse V x = (V Tn0 + γ( ( 2φ f + V x )  2φ f )) 9/17/2005 VLI esign I;. Milenkovic 26 VLI esign I;. Milenkovic 13
14 ascaded NMO Only PTs = = G M 1 = x = V Tn1 G y M 2 = Out = = M 1 x M 2 y Out wing on y = V Tn1 V Tn2 wing on y = V Tn1 Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins 9/17/2005 VLI esign I;. Milenkovic 27 olution 1: Level Restorer Level Restorer =1 M 2 Out=0 =0 M n M r x= 0 1 For correct operation M r must be sized correctly (ratioed) off M 1 Out =1 Full swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when is high on 9/17/2005 VLI esign I;. Milenkovic 28 VLI esign I;. Milenkovic 14
15 Transient Level Restorer ircuit Response 3 W/L 2 =1.50/0.25 W/L n =0.50/0.25 W/L 1 =0.50/0.25 Voltage, V 2 1 W/L r =1.75/0.25 W/L r =1.50/0.25 node x never goes below V M of inverter so output never switches 0 W/L r =1.0/0.25 W/L r =1.25/ Time, ps Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases t r (but decreases t f ) 9/17/2005 VLI esign I;. Milenkovic 29 olution 2: Multiple V T Transistors Technology solution: Use (near) zero V T devices for the NMO PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to ) low V T transistors In 2 = 0V = 2.5V on Out In 1 = 2.5V off but leaking = 0V sneak path Impacts static power consumption due to subthreshold currents flowing through the PTs (even if V G is below V T ) 9/17/2005 VLI esign I;. Milenkovic 30 VLI esign I;. Milenkovic 15
16 olution 3: Transmission Gates (TGs) Most widely used solution = = = = = = Full swing bidirectional switch controlled by the gate signal, = if = 1 9/17/2005 VLI esign I;. Milenkovic 31 olution 3: Transmission Gates (TGs) Most widely used solution = = = = = = Full swing bidirectional switch controlled by the gate signal, = if = 1 9/17/2005 VLI esign I;. Milenkovic 32 VLI esign I;. Milenkovic 16
17 Resistance of TG R n W/L p =0.50/0.25 0V R p Resistance, kω R p 2.5V V out R n 2.5V R eq W/L n =0.50/ V out, V 9/17/2005 VLI esign I;. Milenkovic 33 TG Multiplexer F In 2 F In 1 F =!(In 1 + In 2 ) In 1 In 2 9/17/2005 VLI esign I;. Milenkovic 34 VLI esign I;. Milenkovic 17
18 Transmission Gate OR 9/17/2005 VLI esign I;. Milenkovic 35 Transmission Gate OR weak 0 if! 0 1 on off on off!! weak 1 if an inverter 9/17/2005 VLI esign I;. Milenkovic 36 VLI esign I;. Milenkovic 18
19 TG Full dder in um out 9/17/2005 VLI esign I;. Milenkovic 37 ifferential TG Logic (PL) F= F= F= F= N/NN OR/NOR 9/17/2005 VLI esign I;. Milenkovic 38 VLI esign I;. Milenkovic 19
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