Review. EECS Components and Design Techniques for Digital Systems. Lec 18 Arithmetic II (Multiplication) Computer Number Systems

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1 Review EE 5 - omponents and Design Techniques for Digital ystems Lec 8 rithmetic II (Multiplication) David uller Electrical Engineering and omputer ciences University of alifornia, Berkeley ircuit design for unsigned addition Full per bit slice Delay limited by arry Propagation» Ripple is algorithmically slow, but wires are short arry select imple, resource-intensive Excellent layout arry look-ahead Excellent asymptotic behavior Great at the board level, but wire length effects are significant on chip Digital number systems How to represent negative numbers imple operations lean algorithmic properties 2omplement is most widely used ircuit for unsigned arithmetic ubtract by complement and in Overflow when cin xor cout of sign-bit is omputer Number ystems Positional notation D n- D n-2 D represents D n- B n- D n-2 B n-2 D B where D i {,, B- } 2s omplement D n- D n-2 D represents: - D n- 2 n- D n-2 2 n-2 D 2 MB has negative weight s omplement Overflow How can you tell an overflow occurred? = -8! -7-2 = 7! 2omp. Overflow Detection 2s omplement dder/ubtractor 3 B 3 B 3 2 B 2 B 2 B B B B el el el el B B B B O I O I O I O I 3 2 Overflow!"#!! dd/ubtract

2 dders on the Xilinx Virtex arry Look-ahead dders Dedicated logic provides fast arithmetic capability for highspeed arithmetic functions. The Virtex-E LB supports two separate chains, one per lice. The height of the chains is two bits per LB. The arithmetic logic includes an XOR gate and ND gate that allows a 2- bit full to be implemented within a slice. in to out delay =.ns, versus.4ns for F to X delay. How do we map a 2-bit to one slice? In general, for n-bit addition best we can achieve is delay α log(n) How do we arrange this? (think trees) First, reformulate basic stage: a b c i c i s kill k i = b i propagate p i = b i generate g i = b i c i = g i p i c i s i = p i c i arry Look-ahead dders in blocks Group propagate and generate signals: p i g i p i g i p ik g ik c in P = p i p i p ik G = g ik p ik g ik- (p i p i2 p ik )g i c out arry Look-ahead dders a b a b a 2 b 2 a 3 b 3 a 4 b 4 a 5 b 5 a b c P a G a c 3 = G a P a c P b G b 9-bit Example of hierarchically generated P and G signals: P = P a P b P c P true if the group as a whole propagates a to c out G true if the group as a whole generates a out = G P in Group P and G can be generated hierarchically. a 6 b 6 a 7 b 7 a 8 b 8 c P c G c G = G c P c G b P b P c G a c 9 = G Pc c 6 = G b P b c 3 Parallel Prefix (generalizing L) x B B Bx B x a b s c c a b s a 2 b 2s2 c 3 a 3 b 3s3 a 4 b 4s4 p,g c c 2 c c 4 c b isi c i c i p,g p = a b g = ab s = p c i c i = g c i p 8-bit arry Lookahead dder c 5 a 5 b 5s5 a 6 b 6s6 c 7 a 7 b 7s7 c 6 c c 8 P a,g a P b,g b c in c out P = P a P b G = G b G a P b out = G c in P ompute all the prefixes F i = F i- op F i-2 op op F ssume associative and commutative

3 Time / pace (resource) Trade-offs arry select and L utilize more silicon to reduce time. an we use more time to reduce silicon? How few Fs does it take to do addition? Bit-serial dder B lsb reset FF F, B, and R held in shiftregisters. hift right once per clock cycle. Reset is asserted by controller. n-bit shift register c s R ddition of 2 n-bit numbers: takes n clock cycles, uses FF, F cell, plus registers the bit streams may come from or go to other circuits, therefore the registers may be optional. Requireontroller What does the FM look like? Implemented? Final out? nnouncements Basic concept of multiplication Reading: 5.8 Regrades in with homework on Friday Digital Design in the news from UB Organic e-textiles (Prof. Vivek ubramanian) $ ' $ "# % "# "&# product of 2 n-bit numbers is an 2n-bit number sum of n n-bit partial products unsigned ( ombinational Multiplier: accumulation of partial products () ( (& ( ( ( ( rray Multiplier Generates all n partial products simultaneously. b3 b2 b b a a P P Each row: n-bit with ND gates out b j F sum in sum out in What is the critical path?

4 hift and dd Multiplier n-bit P B n-bit register ost α n, Τ = n clock cycles. What is the critical path for determining the min clock period? ums each partial product, one at a time. In binary, each partial product is shifted versions of or. ontrol lgorithm:. P, multiplicand, B multiplier 2. If LB of B== then add to P else add 3. hift [P][B] right 4. Repeat steps 2 and 3 n- times. 5. [P][B] has product. arry-save ddition peeding up multiplication is a matter of speeding up the summing of the partial products. arry-save addition can help. arry-save addition passes (saves) the carries to the output, rather than propagating them. -save add -propagate add Example: sum three numbers, 3 =, 2 =, 3 = 3 2 c = 4 s = 3 c = 2 s = 6 = 8 -save add In general, -save addition takes in 3 numbers and produces 2. Whereas, -propagate takes 2 and produces. With this technique, we can avoid propagation until final addition arry-save ircuits rray Mult. using arry-save ddition b3 b2 b b F F F F F F F F c When adding sets of numbers, -save can be used on all but the final sum. tandard ( propagate) is used for final sum. x x x 2 a a P P out b j F sum in sum out in P Fast propagate nother Representation (from book) um In X in $*! Y F B O I out um Out 3 2 B 3 B 2 B B B B 3 B 2 B B B B2 3 B2 2 B2 B2 B2 B3 3 B3 2 B3 B3 B3 dd P P P &,&- $* arry-save ddition is associative and communitive. For example: (((X X ) X 2 ) X 3 ) = ((X X ) ( X 2 X 3 )) x 7 x 6 x 5 x 4 x 3 x 2 x x P log 2 N log 3/2 N balanced tree can be used to reduce the logic delay. This structure is the basis of the Wallace Tree Multiplier. Partial products are summed with the tree. Fast P (ex: L) is used for final sum. Multiplier delay α log 3/2 N log 2 N

5 igned Multiplier igned multiplication igned Multiplication: Remember for 2 omplement numbers MB has negative weight: N 2 i n X = x i 2 xn 2 i= ex: = 2 = = = $ - () * (-5) () () -(-24) Note: 2omplement ign extension "# Therefore for multiplication: a) subtract final partial product b) sign-extend partial products Modifications to shift & add circuit: a) /subtractor b) sign-extender on P shifter register product of 2 n-bit numbers is an 2n-bit number sum of n n-bit partial products unsigned igned rray Multiplier hift and dd igned Multiplier Implicit ign extension b3 b2 b b a P a P n-bit P B n-bit register igned extend partial product at each stage Final step is a subtract ummary 2 complement number systems lgebraic and corresponding bit manipulations Overflow detection ignficance of sign bit -2 n- arry look ahead is form a parallel prefix Time / pace tradeoffs Bit serial Binary Multiplication algorithm rray multiplier erial multiply (with bit parallel ) igned multiplication ign extend multipicand ign bit of multiplier treated as subtract