Integer Multipliers 1

Transcription

1 Integer Multipliers

2 Multipliers must have circuit in most DS applications variety of multipliers exists that can be chosen based on their performance Serial, Serial/arallel,Shift and dd, rray, ooth, Wallace Tree,. 2

3 converter reset en R en reset reset en 6x6 multiplier RC Converter converter R 3

4 Multiplication lgorithm = n- n-2 Multiplicand Y=Yn- Yn-2.Y Multiplier Yn- Yn-2 Yn-3 Y Y Yn- Yn-2 Yn-3 Y Y Yn-2 Yn-22 Yn-32 Y2 Y Yn-n-2 Yn-2 n-2 Yn-3 n-2 Yn-2 Yn-2 Yn-n- Yn-2n- Yn-3n- Yn- Yn n- 2n-2 2n-3 2 4

5 . Multiplication lgorithms Implementation of multiplication of binary numbers boils down to how to do the the additions. Consider the two 8 bit numbers and to generate the 6 bit product. First generate the 64 partial roducts and then add them up The equation is :. (m n) (m)(n) m n i j a b i j 2 i j 5

6 Multiplier Design R E G I N Storage MU (66 Multiplier Unit) Control Unit R E G O U T 6

7 : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= G2 CLK d -bit REG q x y G x y + x y Serial Register CLK CLK/(N+) Slide 7

8 S i : the ith bit of the final result : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= G2 CLK d -bit REG q x y G x y + x y S Serial Register CLK CLK/(N+) Slide 2 8

9 S i : the ith bit of the final result : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= G2 CLK d -bit REG q x 2 y G x 2 y + x 2 y x y S Serial Register CLK CLK/(N+) Slide 3 9

10 S i : the ith bit of the final result : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= G2 CLK d -bit REG q x 3 y G x 3 y + x 3 y x 2 y x y S Serial Register CLK CLK/(N+) Slide 4

11 S i : the ith bit of the final result : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S G2 CLK d -bit REG q G + x 3 y x 2 y x y Serial Register S CLK CLK/(N+) Slide 5

12 S i : the ith bit of the final result C i : the only carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= x y G2 CLK d -bit REG q x y x y G x y + C S x 3 y x 2 y Serial Register x y S CLK CLK/(N+) Slide 6 2

13 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= x 2 y G2 CLK d -bit REG q x 2 y C 2 + S 2 S x 3 y x 2 y S x y G x y C Serial Register CLK CLK/(N+) Slide 7 3

14 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= x 3 y G2 CLK d -bit REG q x 3 y C 3 x 2 y G x 2 y + C 2 S 3 S 2 S Serial Register x 3 y S CLK CLK/(N+) Slide 8 4

15 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= G2 CLK d -bit REG q x 3 y G x 3 y + C 4 C 3 S 4 S 3 S 2 S Serial Register S CLK CLK/(N+) Slide 9 5

16 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S G2 CLK d -bit REG q G + C 5 = C 4 S 5 S 4 S 3 S 2 Serial Register S S CLK CLK/(N+) Slide 6

17 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S 2 G2 CLK d -bit REG q x S 2 y G x y C 2 S 2 S 5 S 4 S 3 Serial Register S 2 S S CLK CLK/(N+) Slide 7

18 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S 3 G2 CLK d -bit REG q x S 3 y G x y C 3 S 3 C 2 S 2 S 5 S 4 Serial Register S 3 S S CLK CLK/(N+) Slide 2 8

19 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S 4 G2 CLK d -bit REG q x 2 S 4 y G x 2 y C 4 S 4 C 3 S 3 S 2 S 5 Serial Register S 4 S S CLK CLK/(N+) Slide 3 9

20 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S 5 G2 CLK d -bit REG q x 3 S 5 y G x 3 y C 5 S 5 C 4 S 4 S 3 S 2 Serial Register S 5 S S CLK CLK/(N+) Slide 4 2

21 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S 2 G2 CLK d -bit REG q G + C 6 = S 6 C 5 S 5 S 4 S 3 Serial Register S 2 S S CLK CLK/(N+) Slide 5 2

22 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S 3 G2 CLK d -bit REG q S 3 x y G x y C 3 2 S 3 S 6 S 5 S 4 Serial Register S 3 S 2 S S CLK CLK/(N+) Slide 6 22

23 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S 4 G2 CLK d -bit REG q S 4 x y G x y C 4 2 S 4 2 C 3 S 3 S 6 S 5 Serial Register S 4 S 2 S S CLK CLK/(N+) Slide 7 23

24 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S 5 G2 CLK d -bit REG q S 5 x 2 y G x 2 y C 5 2 S 5 2 C 4 S 4 S 3 S 6 Serial Register S 5 S 2 S S CLK CLK/(N+) Slide 8 24

25 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S 6 G2 CLK d -bit REG q S 6 x 3 y G x 3 y C 6 S 6 2 C 5 S 5 S 4 S 3 Serial Register S 6 S 2 S S CLK CLK/(N+) Slide 9 25

26 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= S 3 G2 CLK d -bit REG q G + S 7 C 6 S 6 S 5 S 4 Serial Register S 3 S 2 S S CLK CLK/(N+) Slide 2 26

27 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= G2 CLK d -bit REG q G + S 7 S 6 S 5 Serial Register S 4 S 3 S 2 S S CLK CLK/(N+) Slide 2 27

28 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i : x 3 x 2 x x Y:y 3 y 2 y y Input Sequence for G: x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x x 3 x 2 x x y 3 y 3 y 3 y 3 y 2 y 2 y 2 y 2 y y y y y y y y Reset: Reset= G2 CLK d -bit REG q G + S 7 S 6 S 5 Serial Register S 4 S 3 S 2 S S CLK CLK/(N+) Slide 2 28

29 S i : the ith bit of the final result y y y 2 y 3 x S S S S S Slide 29

30 S i : the ith bit of the final result C i : the only carry from column i y y y 2 y 3 x x x y x y S C S S S S Slide 2 3

31 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i y y y 2 y 3 x 2 x x x 2 y x y x y 2 S S 2 S 2 S 2 S S C 2 C 2 C Slide 3 3

32 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i y y y 2 y 3 x 3 x 2 x x x 3 y x 2 y x y 2 x y 3 S 3 S 3 S C 3 C 3 C 3 2 S 3 S 2 S S C 2 C 2 Slide 4 32

33 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i y y y 2 y 3 x 3 x 2 x x 3 y x 2 y 2 x y 3 S 4 S 4 S S 4 S 3 S 2 S S C 4 C 4 C 4 2 C 3 C 3 C 3 2 Slide 5 33

34 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i y y y 2 y 3 x 3 x 2 x 3 y 2 x 2 y 3 S 5 S 5 C S 5 S 4 S 3 S 2 S S C 5 C 5 C 4 C 4 C 4 2 Slide 6 34

35 S i : the ith bit of the final result C i : the only carry from column i S ij : the jth partial sum for column i C ij : the jth partial carry from column i y y y 2 y 3 x 3 x 3 y 3 C 5 S S 6 S 5 S 4 S 3 S 2 S S C 6 C 5 C 5 Slide 7 35

36 S i : the ith bit of the final result C i : the only carry from column i y y y 2 y S 7 S 7 S 6 S 5 S 4 S 3 S 2 S S C 6 Slide 8 36

37 Shift dd Multiplier Design Implementation INUT in (7 downto ) REG MU 8 bit dder INUT in (7 downto ) REGC REG CLOCK Result (5 downto 8) Result (7 downto ) 37

38 Synchronous Shift and dd Multiplier controller Multiplication process: 5 states: Idle, Init, Test, dd, and Shift&Count. Idle: Starts by receiving the Start signal; Init: Multiplicand and multiplier are loaded into a load register and a shift register, respectively; Test: The LS in the shift register which contains the multiplier is tested to decide the next state; 38

39 Synchronous Shift and dd Multiplier ControllerDesign dd: If LS is, then next state is to add the new partial product to the accumulation result, and the state machine transits to shift&count state ; Shift&Count: If LS is, then the two shift register shift their contains one bit right, and the counter counts up by one step. fter that, the state machine transits back to test state; When the counter reaches to N, a Stop signal is asserted and the state machine goes to the idle state; Idle: In the idle state, a Done signal is asserted to indicate the end of multiplication. 39

40 n-bit Multiplier: Q =: Multiplicand is added to register ; the result is stored in register ; registers C,, Q are shifted to the right one bit Q =: Registers C,, Q are shifted to the right one bit Multiplicand n-bit dder dd Shift and dd Control Logic Shift Right C n- n... Q n- Q n... Q Q Multiplier Slide 4

41 Example: 4-bit Multiplier Initial Values Multiplicand 4-bit dder dd Shift and dd Control Logic Shift Right Multiplier Slide 2 4

42 Example: 4-bit Multiplier First Cycle--dd Multiplicand 4-bit dder dd= Shift and dd Control Logic Shift Right= Multiplier Slide 3 42

43 Example: 4-bit Multiplier First Cycle--Shift Multiplicand 4-bit dder dd= Shift and dd Control Logic Shift Right= Multiplier Slide 4 43

44 Example: 4-bit Multiplier Second Cycle--Shift Multiplicand 4-bit dder dd= Shift and dd Control Logic Shift Right= Multiplier Slide 5 44

45 Example: 4-bit Multiplier Third Cycle--dd Multiplicand 4-bit dder dd= Shift and dd Control Logic Shift Right= Multiplier Slide 6 45

46 Example: 4-bit Multiplier Third Cycle--Shift Multiplicand 4-bit dder dd= Shift and dd Control Logic Shift Right= Multiplier Slide 7 46

47 Example: 4-bit Multiplier Fourth Cycle--dd Multiplicand 4-bit dder dd= Shift and dd Control Logic Shift Right= Multiplier Slide 8 47

48 Example: 4-bit Multiplier Fourth Cycle--Shift Multiplicand 4-bit dder dd= Shift and dd Control Logic Shift Right= Multiplier Slide 9 48

49 4*4 Synchronous Shift and dd Multiplier Design Layout Design Floor plan of the 4*4 Synchronous Shift and dd Multiplier 49

50 Comparison between Synchronous and synchronous pproaches. 5

51 Example : (simulated by Ovais hmed, Fall_3,project) Multiplicand = 2 = 89 6 Multiplier = 2 = 6 Expected Result = 2 =

52 rray Multiplier Regular structure based on add and shift algorithm. ddition is mainly done by carry save algorithm. Sign bit extension results in a higher capacitive load and slows down the speed of the circuit. 52

53 4*4 Multiplier 3 2 x 3 2 Inputs C x 3 x 2 x x + x 3 x 2 x x C sum sum sum sum + 2 x 3 2 x 2 2 x 2 x Internal Signals C sum sum sum sum + 3 x 3 3 x 2 3 x 3 x C sum sum sum sum Y7 Y6 Y5 Y4 Y3 Y2 Y Y Outputs 53

54 ddition with CL a 3 a 2 a a = a 3 a 2 a a b = b 3 b 2 b b a 3 a 2 a a b C out Four-bit dder C i n a 3 a 2 a a b 2 C out Four-bit dder C in a 3 a 2 a a b 3 C out Four-bit dder C in 54 roduct (*)

55 rray Multiplier with CS ** ij = i j Total of 6 gates j i C i F. S i C i F. S i C i F. S i i j F. F. F. ij C i S i C i S i C i S i F. F. F. C i S i C i S i C i S i 33 F. F. F. C i S i C i S i C i S i 55 R 7 R 6 R 5 R 4 R3 R 2 R R

56 Critical ath with rray Multipliers F F F H F F F H F F F H Two of the possible paths for the Ripple-Carry based 4*4 Multiplier rea = (N*N) ND Gate + (N-)N Full-dder Delay = τ H + (2N-) τ F 56

57 57

58 x 4 y 4 x 3 y 4 x 4 y 3 Wallace Tree x 2 y 4 x 3 y 3 x 4 y 2 x y 4 x 2 y 3 x 3 y 2 x 4 y x y 4 x y 3 x 2 y 2 x 3 y x 4 y x y 3 x y 2 x 2 y x 3 y x y 2 x y x 2 y x y x y x y

59 rray Multiplier + Wallace Tree 59

60 6 9/28/29 Concordia VLSI Lab 6 ackground augh-wooley lgorithm Convert negative partial products to positive representation No sign-extension required ) *2 *2 )*( *2 *2 ( * 2 2 i k i i k k i k i i k k y y x x Y i k k i i k i k k i i k j i k j j i k i k k k x y y x y x y x * *2 ) *2 *2 * (

61 examples of 5-by-5 augh-wooley a 4b ' a a b 3b a 2b a b a 4b ' a 3b F F a2b a b F F a b a 4b 2' a 3b 2 a 2b 2 a b 2 F F F F a b 2 a 4b 3' a F 3b 3 a F 2b 3 a F b 3 F a b 3 a 4' b 4' F a 4b 4 F a 3'b4 F a 2'b4 F a 'b4 F a 'b4 a 4 F F F F F F b The schematic logic circuit diagram of a 5-by-5 augh-wooley two s complement array multiplier 9/28/29 Concordia VLSI Lab 6 6

62 a7 a6 a5 a4 a3 a2 a a * a7 a6 a5 a4 a3 a2 a a a7*a a6*a a5*a a4*a a3*a a2*a a*a a*a a7*a a6*a a5*a a4*a a3*a a2*a a*a a*a a7*a2 a6*a2 a5*a2 a4*a2 a3*a2 a2*a2 a*a2 a*a2 a7*a3 a6*a3 a5*a3 a4*a3 a3*a3 a2*a3 a*a3 a*a3 a7*a4 a6*a4 a5*a4 a4*a4 a3*a4 a2*a4 a*a4 a*a4 a7*a5 a6*a5 a5*a5 a4*a5 a3*a5 a2*a5 a*a5 a*a5 a7*a6 a6*a6 a5*a6 a4*a6 a3*a6 a2*a6 a*a6 a*a6 a7*a7 a6*a7 a5*a7 a4*a7 a3*a7 a2*a7 a*a7 a*a a7*a6 a7*a5 a7*a4 a7*a3 a7*a2 a7*a a7*a a6*a a5*a a4*a a3*a a2*a a*a ' a

63 63 aa a a2a a5a a4a a3a2 a5a a4a2 a6a a6a a5a2 a7a a6a2 a5a3 a7a a3a a4a a2a a2 a3a a a3 a3a4 a4 a6a3 a5a4 a7a2 a5 a6a4 a7a3 a6a5 a6 a7a4 a7a5 a7 a7a6 S S S2 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S3 Example of an 8bit squarer N*N N=8bits

64 rray Multiplier 32bits by 32bits multiplier 64

65 ooth (Radix-4) Multiplier Radix-4 (3 bit recoding) reduces number of partial products to be added by half. Great saving in area and increased speed. = -a n- 2 n- + a n-2 2 n-2 + a n-3 2 n a 2 + a = -b n- 2 n- + b n-2 2 n-2 + b n-3 2 n b 2 + b ase 4 redundant sign digit representation of is = (n/2) - i = 2 2i K i 65

66 K i is calculated by following equation K i = -2b 2i+ + b 2i + b 2i- i =,,2,.(n-2)/2 3 bits of Multiplier, b 2i+, b 2i, b 2i-, are examined and corresponding K i is calculated. is always appended on the right with zero (b - = ), and n is always even ( is sign extended if needed). The product is then obtained by adding n/2 partial products. (n/2) - = = i = 2 2i K i 66

67 ooth lgorithm Decoding of multiplier to generate signals for hardware use i+ i i- O NEG ZERO TWO

68 ooth lgorithm ooth recoded multiplier examines Three bits of the multiplicand at a time It determine whether to add zero,, -, 2, or -2 of that rank of the multiplicand. The operation to be performed is based on the current two bits of the multiplicand and the previous bit i+ i- Z i/

69 IT OERTION M is multiplied by i i+ i+2 add zero (no string) + add multipleic (end of string) + add multiplic. (a string) + add twice the mul. (end of string) +2 sub. twice the m. (beg. of string) -2 sub. the m. (-2 and +) - sub. the m. (beg. of string) - sub. zero (center of string) - 69

70 ooth lgorithm-a higher radix Multiplication Multiplicand = Multiplier = ( )( ) artial product bits ( ) 2 4 artial product bits ( 3 2 )4 roduct = 7

71 Example The following example is used to show how the calculation is done properly. Multiplicand = Multiplier Y = dded to the multiplier fter booth decoding, Y is decoded as to multiply by +2, -, + separately, then shift the partial product two bits and add them together. * + * - *

72 Sign Extension 72

73 Sign extension Traditional sign-extension scheme Segment the input operands based on the size of embedded blocks Multiply the segmented inputs and extend the sign bit of each partial products Sum all partial products Sign extension Segmented input operands + partial products Sign Final result 9/28/29 Concordia VLSI Lab 73 73

74 ooth lgorithm-example Example : (+3) (+29) (+87) 74

75 ooth lgorithm Example 2 Notice sign extensions 2s complement of multiplicand (-3) (+29) (-87) 75

76 ooth lgorithm-example 3 Notice the sign extensions (-3) (-29) Shifted 2s complement (+87) 76

77 Comparison of ooth and parallel multiplier shift and dd 77

78 Template to reduce sign extensions for ooth lgorithm For hardware implementation lease note that each operand is 7 bit ie. the 7 th bit is the sign bit. lso negative numbers are entered as s complement, this is why you need to add the S in the right hand side of the diagram. If you use 2 complement then the S s on right side of the diagram can be removed 78

79 Comparison of Template and the sign extension S S S S S S S S S S S 2 S 2 S 2 S 2 S 2 S 2 S 3 S 3 S 3 S 3 S 4 Sign template Sign extension 79

80 S S S S S S S S S S artial roduct matrix generated for a 6 * 6 bit multiplication, Using booth and the template given in previous slide

81 Example of using the template 25 * - 35 with -35 as the multiplier. Using 8 bit representation Using the Template 25 * -35 Sign bit dd SS dd inverted S dd Inverted sign and add * dd Inverted sign bit * - * 2 No sign bit * - This is a ve number. Convert it = 875 8

82 ooth Multiplier Components Multiplier ooth Encoder Mu lt ip li ca nd U (artial products unit) (artial products adding unit) roduct 82

83 Wallace Tree and Ripple Carry dder Structure. Of 8*8 multiplier With ipeline artial roduct,,2(5 downto ) artial roduct 3(5 downto ) Ripple Carry dder ipeline Register Critical ath

84 CLK Start Mulbegin Hardware implementation of ooth with shift and add Init LD Doubleshift SH CLK 2s complement Init Shift CLK D LD SH D CLK CLK 6 reg_2left CLR Start Start Q Q CLRreg2right7 *2 (shifter) 7 =; 6= =, 6= endcheck Mul C 32 D 32 ctrl F Stop Q(-2) CLK Mul2 ctrl Y 32 mux4-32 Mulbegin Stop 3bit CLK sign expansion CLR Start Shift not used Mux Mux2 Mux Init Mulend Cout 37 FSM Sum Cin dder 37 Start Doubleshift Mux Mux2 CLK Mux Init Mulend 37 Mux Sel CLK Counter2 Y Mux37 CLR Start D 37 Q 37 CLK Register37 Finish CLR Start Finish Mulend Result Init Shift CLK D LD SH CLK 6 32 Q *2 (shifter) reg_2left32 CLR Start 84

85 Simulation lan 32-bit Signal Generator [3:] ehavioral Multiplier * [63:] Result 64-bit Comparator 32-bit Signal Generator [3:] My Multiplier My_[63:] Failed Number rray Multiplier Modified ooth Multiplier Wallace Tree Multiplier Modified ooth- Wallace Tree Multiplier Twin ipe Serial-arallel Multiplier 85

86 Testing the Design 86

87 Simulation For arallel Multipliers Signed Number: Unsigned Number: 87

88 Simulation For Signed S/ Multipliers There are 34 ns delay between the result and the operators because of the D flip-flops delay. 88

89 FG after implementation, areas of programming shown clearly 89

90 nother implementation of the above after pipelining, the place and rout has paced the design in different places. 9

91 Spartacus FG board 9

92 Testing the multiplication system 92

93 Comparison of Multipliers rea Total CL s (#) Maximum Delay D(ns) Total Dynamic ower (W) Delay ower roduct (D) (ns W) rea ower roduct () (# W) rea Delay roduct (D) (# ns) rea Delay 2 roduct (D 2 ) (# ns 2 ) rray Multiplier Modified ooth Multiplier Wallace-Tree Multiplier Modified ooth- Wallace Tree Multiplier Twin ipe Serial- arallel Multiplier ehavioral Multiplier (3.36x32) E E+4 6.3E E E+4.48E E+6.58E+6.9E+6 9.8E E E+6 93 Table 7. erformance comparison for two s complement multipliers y Chen Yaoquan, M.Eng. 25

94 Comparison of Multipliers rray Multiplier Modified ooth Multiplier Wallace-Tree Multiplier Modified ooth- Wallace Tree Multiplier Twin ipe Serial- arallel Multiplier ehavioral Multiplier rea Total CL s (#) Maximum Delay D(ns) Total Dynamic ower (W) Delay ower roduct (D) (ns W) rea ower roduct () (# W) rea Delay roduct (D) (# ns) rea Delay 2 roduct (D 2 ) (# ns 2 ) E+5 7.9E E E E+4.34E E+6.8E+6.9E E E E+6 94 Table 7. erformance comparison for Unsigned multipliers y Chen Yaoquan, M.Eng. 25

95 rea (#) Comparison of Multipliers Change the value of set_max_delay in Script file (ns) >6 rea(#) ower(w) Delay(n s) The relation of rea and Delay for behavioral multiplier Series "banana curve" Delay (ns) 95

96 Comparison of Multipliers rray Multiplier Modified ooth Multiplier Wallace- Tree Multiplier Modified ooth- Wallace Tree Multiplier Twin ipe Serial- arallel Multiplier ehavioral Multiplier rea Medium Small Large Small Smallest Medium Critical Delay Medium Fast Very Fast Fastest Very Large Large ower Consumption Large Medium Large Medium Smallest Medium Complexity Simple Complex More Complex More Complex Simple Simplest Implement Easy Medium Difficut Difficut Easy Easiest y Chen Yaoquan, M.Eng

97 ipelining Simulation 97

98 Synthesis for Signed Multipliers rray Modified ooth Wallace Tree Modified ooth -Wallace Tree Twin ipe S/ ehavioral 98

99 Synthesis for Unsigned Multipliers rray Modified ooth Wallace Tree Modified ooth -Wallace Tree Twin ipe S/ ehavioral 99

100 Conclusion Modified ooth and Wallace Tree are the best techniques for high speed multiplication. Wallace Tree has the best performance, but it is hard to implement. ooth algorithm based multipliers have lower area among parallel multipliers. For behavioral multipliers, the area will increase while the delay decreases.

101 Comparison rea Total CL s (#) rray Multiplier Modified ooth Multiplier Wallace Tree Multiplier Modified ooth & Wallace Tree Multiplier Twin ipe Serial- arallel Multiplier Maximum Delay (ns) 87.87ns 39.4ns.4ns.43ns 22.58ns (722.56ns) ower Consumption at highest speed (mw) Delay ower roduct (D) (ns mw) rea ower roduct () (# mw) rea Delay roduct (D) (# ns) rea Delay 2 roduct(d 2 ) (# ns 2 ) 6.656m W (at 88ns) 23.36mW (at 4ns) 3.95mW (at.4ns) 3.862mW (at.43ns) 2.89mW (at ns) x x x x x 8.8 x x x x x 25. x x x x 6 6

102 NOTICE The rest of these slides are for extra information only and are not part of the lecture 2

103 rray ddition 3

104 ddition of 8 binary numbers using the Wallace tree principal 4

105 5

106 6

107 FINISH EGIN CLK RESET MULT32 Done COUNTER2 INVERTER CLR RESULT 32 dder ND_2 CLK D 37 Q END LST_RESULT STRT CLR REGSTER37 7

108 augh-wooley two's complement multiplier: a4b' a4b' ab a3b a2b ab a3b F F a2b F ab F ab a4b2' a3b2 a2b2 ab2 F F F F ab2 a4b3' F F F a3b3 a2b3 ab3 F ab3 a4' b4' F a4b4 F a3'b4 F a2'b4 F a'b4 F a'b4 a4 F F F F F F b The schematic logic circuit diagram of a 5-by-5 augh-wooley two s complement array multiplier 8

109 a 4 a 3 a 2 a a b 4 b 3 b 2 b b a 4b ' a 3b a 2b a b a b a 4b ' a 3b a 2b a b a b a 4b 2' a 3b 2 a 2b 2 a b 2 a b 2 a 4b 4 a 4b 3' a 3b 3 a 2b 3 a b 3 a b 3 a 4' a 3'b 4 a 2'b 4 a 'b 4 a 'b 4 + b 4' a 4 b 4 p9 p8 p7 p6 p5 p4 p3 p2 p p =3 = -5 = -5 =3 + + = -65 = -65 =3 = 5 = -3 = -5 + = 65 + = 65 9

110 Cluster Multipliers Divide the multiplier into smaller multipliers

111 Cluster Multipliers Multiplier Multiplicand 8~7 3~ 8~7 3~ bit Latch 8-bit Latch 8-bit Latch 8-bit Latch 4-bit Multiplier CLK 4-bit Multiplier CLK 4-bit Multiplier CLK 4-bit Multiplier CLK The circuit used to generate the enable signal /CLR 8-bit Latch EN3 EN2 EN EN CLK /CLR 8-bit Latch CLK /CLR 8-bit Latch CLK /CLR 8-bit Latch CLK Final ddition Stage 6 8-bit cluster low power multiplier

112 Cluster Multipliers Dividing the multiplication circuit into clusters (blocks) of smaller multipliers pplying clock gating techniques to disable the blocks that are producing a zero result. Features Low ower (claims 3.4 % savings) 2

113 Multiplexer-ased rray Multipliers Z 4 Z 3 Z 2 Z Z 4 Z 3 Z 2 Z j 2 Z 4 2 Z 3 3 Z 4 xjyj n j x j y j 2 2 j n j Z j 2 j Z j x jyj j y j j j j

114 Multiplexer-ased rray Multipliers Two types of cells: Cell : produce the terms Z ij 2 j carry save adder array and includes a full adder of Cell 2: produce the terms x j y j 2 j and includes a full adder of carry save adder array 4

115 Multiplexer-ased rray Multipliers Characteristics Faster than Modified ooth Unlike ooth, does not require encoding logic Requires approximately N 2 /2 cells Has a zigzag shape, thus not layout-friendly 5

116 Multiplexer-ased rray Multipliers Improvement More rectangular layout Save up to 4 percent area without penalties Outperforms the modified ooth multiplier in both speed and power by 3% to 26% 6

117 Gray-Encoded rray Multiplier Dec Hyb Dec Hyb Dec Hyb Dec Hyb s complement Hybrid Coding Having a single bit different for consecutive values Reducing the number of transitions, and thus power ( for highly correlated streams ). 7

118 Gray-Encoded rray Multiplier n 8-bit wide 2 s complement radix-4 array multiplier 8

119 Gray-Encoded rray Multiplier Characteristics Uses gray code to reduce the switching activity of multiplier Saves 45.6% power than Modified ooth Uses greater area(26.4% ) than Modified ooth 9

120 Ultra-high Speed arallel Multiplier How to ultra-high speed? ased on Modified ooth lgorithm and Tree Structure (Column compress) Chooses efficient counters (3:2 and 5:3) Uses the new compressor (faster 2% ) Uses First artial product ddition (F) lgorithm (reducing the bits of CL by 5%) 2

121 Ultra-high Speed arallel Multiplier Divide into 3 rows or 5 rows only (most efficient). Calculate the partial products as soon as possible. The final CL is only 6-bit instead of 32-bit. Calculation process using parallel counter in case of 6x6 ---Totally reduce delay by about 3% 2

122 ULLRLF Multiplier ULLRLF stands for Upper/Lower Left-to- Right Leapfrog. Combine the following techniques: Signal flow optimization in [3:2] adder array for partial product reduction, Left-to-right leapfrog (LRLF) signal flow, Splitting of the reduction array into upper/lower parts. 22

123 ULLRLF Multiplier ij is always connected to pin Sin/Cin are connected to /C, most Sin signals are connected to C ) Signal flow optimization in [3:2] adder array -- For n = 32, the delay is reduced by 3 percent. -- The power is saved also. 23

124 ULLRLF Multiplier The sum signals skip over alternate rows. 2) Left-to-Right Leapfrog (LRLF) Structure -- The delay of signals is more balanceable. -- Low power. 24

125 ULLRLF Multiplier Only n+2 bits 3) Upper/Lower Split Structure -- The long path of data path be broken into parallel short paths, there would be a saving in power. -- The delay of artial roducts Reduction is reduced. 25

126 ULLRLF Multiplier ULLRLF multipliers have less power than optimized tree multipliers for n 32 while keeping similar delay and area. With more regularity and inherently shorter interconnects, the ULLRLF structure presents a competitive alternative to tree structures. Floorplan of ULLRLF (n = 32) 26

127 Signed rray Multiplier One stage of carry save adder F F F F H F F F F F H STGE 4 TO 3 (Each stage includes 32 ND gates, 3 full adders, half adder and NOT gate) F F F H H 32-bit carry look ahead adder *32-it rray Multiplier for Signed Number 27

128 Unsigned rray Multiplier One stage of carry save adder H F F F H F F F F F H STGE 4 TO 3 (Each stage includes 32 ND gates, 3 full adders and half adder) F F F H 32-bit carry look ahead adder *32-it rray Multiplier for Unsigned Number 28

129 Signed Modified ooth Multiplier E... E E... 6 rows of partial products E... E... E... E... E... E... E... E... E... E... E... E... E. E...S.... E..S... E = The inversion of sign bit in each row S = the i+ bit in the three encoded bits 32*32-bit ooth Multiplier for Signed Number { { { { { { { { { { { { { { { {... M u l t I p l i e r LS i- i+ MS 29

130 Signed Modified ooth Multiplier 3 3 SEL 3 SEL SEL SEL SEL SEL SEL SEL [] 2[] INVERT ooth Encoder [:] One stage SEL SEL SEL SEL 2 SEL SEL SEL SEL [] 2[] INVERT ooth Encoder [3:] H F H H H H H SEL SEL SEL SEL SEL SEL SEL SEL SEL INVERT2 [2] 2[2] INVERT2 ooth Encoder [5:3] H F F F F F F F STGE 3 TO 5 (Each stage includes 33 selectors, 3 full adders, half adder and NOT gate) INVERT n [n] 2[n] INVERT n ooth Encoder [3:5] INVERT INVERT 64-bit carry look ahead adder *32-it Modified ooth Multiplier for Signed Number 3

131 Unsigned Modified ooth Multiplier S'... S' S'... 7 rows of partial products S'... S'... S'... S'... S'... S'... S'... S'... S'... S'... S'... S'... S'. S'...S......S S = the i+ bit in the three encoded bits S' = The inversion of S 32*32-bit ooth Multiplier for unsigned Number { { { { { { { { { { { { { { { { {... i- i+ M u l t i p l i e r LS MS 3

132 Unsigned Modified ooth Multiplier S[] 3 SEL_ END 3 SEL SEL SEL SEL SEL SEL SEL_ END [] 2[] S[] ooth Encoder [:] One stage S[] SEL_ END SEL SEL SEL 2 SEL SEL SEL SEL_ END [] 2[] S[] ooth Encoder [3:] H F H H H H H H S[2] SEL_ END SEL SEL SEL SEL SEL SEL SEL SEL_ END [2] 2[2] S[2] ooth Encoder [5:3] S[2] H F F F F F F F F STGE 3 TO 5 (Each stage includes 33 selectors, 32 full adders, half adder and NOT gate) S[i] [i] 2[i] S [i] ooth Encoder [i+, I, i-] SEL_ END SEL SEL SEL SEL SEL_ END [6] 2[6] S[6] ooth Encoder [3] S6 H F F F F F S[] S[] 64-bit carry look ahead adder *32-it Modified ooth Multiplier for Unsigned Number 32

133 Wallace Tree multipliers [3:] [3:] 32 partial products added in Wallace Tree dder C[63:] S[63:] 64-bit Carry Look-ahead dder [63:] 33

134 Wallace Tree multipliers... Use the 3:2 counters and 2:2 counters Number of levels of = log (32/2) / log (3/2) 8 Irregular structure Fast Input: Output:... Carry 2:2 counter Sum... 3:2 counter Sum Carry

135 Wallace Tree multipliers Carry ropagate/generate unit Cin G63... G G63-G G7-G 8-it CL 8-it CL 8-it CL 8-it CL 8-it CL 8-it CL 8-it CL 8-it CL 2-level hierarchical C63-C56 M7 C56 GM7 C55-C48 C47-C4 C39-C32 C3-C24 C23-C6 C5-C8 M6 M5 M4 M3 M2 M C48 C4 C24 C6 GM6 GM5 GM4 GM3 GM2 GM C8 M GM C7-C 8-it CL C63... C 64-it Summation Unit C64 S63... S 64-it Carry Look head dder 35

136 Modified ooth-wallace Tree Multipliers 36

137 Modified ooth-wallace Tree Multipliers Use the 3:2 counters and 2:2 counters Number of levels of = log (6/2) / log (3/2) 6 Irregular structure Fast Less area Rearrage Dot Matrix of ooth-wallace Multiplier for Signed Number 37

138 Twin pipe serial-parallel multipliers arallel in serial out shift registers Serial in parallel out shift registers bit twin pipe serial-parallel multiplier unit arallel in serial out shift registers Serial in parallel out shift registers Result_ready Load/Shift Reset Clock Sign lock diagram of 32*32-bit signed twin pipe serial-parallel multiplier with serial/parallel conversion logic 38

139 Signed twin pipe serial-parallel multipliers Even data bits on rising clock reset D rising_edge F F D falling_edge F D H Even product D D D D D Repeat 28 units more D D D MU roduct D D D D F F F D H Clock Odd data bits on rising clock... 3 reset D Odd product Sign Reset Clock 32*32-bit twin pipe serial-parallel multiplier for signed number Sign control line and the sign-change hardware 39

140 Unsigned twin pipe serial-parallel multipliers Even data bits on rising clock reset D rising_edge H F D falling_edge F D H Even product D D D D D Repeat 28 units more D D D MU roduct D D D D H F F D H Clock Odd data bits on rising clock... 3 reset Odd product 3 3 Reset Clock 32*32 bit twin pipe serial-parallel multiplier for unsigned number Don t need the Sign control line and the sign-change hardware 4