Digital Integrated Circuits A Design Perspective. Arithmetic Circuits

Transcription

1 Digital Integrated Circuits Design Perspective rithmetic Circuits Reference: Digital Integrated Circuits, 2nd edition, Jan M. Rabaey, nantha Chandrakasan and orivoje Nikolic Disclaimer: slides adapted for INE5442/EEL7312 by José L. Güntzel from the book s companion slides made available by the authors. 1

2 Generic Digital Processor MEM ORY INPUT-OUTPUT CONTROL DTPTH 2

3 uilding locks for Digital rchitectures rithmetic unit - it-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RM, ROM, uffers, hift registers Control - Finite state machine (PL, random logic.) - Counters Interconnect - witches - rbiters - us 3

4 n Intel Microprocessor 9-1 Mux 5-1 Mux a CRRYGEN g64 node1 ck1 UMEL REG sum sumb to Cache 9-1 Mux 2-1 Mux b UMGEN + LU s0 s1 LU : Logical Unit 1000um Itanium has 6 integer execution units like this 4

5 it-liced Design Control it 3 Data-In Register dder hifter Multiplexer it 2 it 1 it 0 Data-Out Tile identical processing elements 5

6 it-liced Datapath From register files / Cache / ypass Multiplexers hifter dder stage 1 Loopback us Loopback us Wiring dder stage 2 Wiring Loopback us it slice 63 dder stage 3 um elect it slice 2 it slice 1 it slice 0 To register files / Cache 6

7 Itanium Integer Datapath Fetzer, Orton, ICC 02 7

8 dders 8

9 Full-dder Cin Full adder um Cout 9

10 The inary dder Cin Full adder um Cout = = C o =

11 Express um and Carry as a function of P, G, D Define 3 new variable which ONLY depend on, Generate (G) = Propagate (P) = Delete = Can also derive expressions for and C o based on D and P Note that we will be sometimes using an alternate definition for Propagate (P) = + 11

12 The Ripple-Carry dder ,0 C o,0 C o,1 C o,2 C o,3 F F F F (=,1 ) Worst case delay linear with the number of bits t d = O(N) t adder = (N-1)t carry + t sum Goal: Make the fastest possible carry path circuit 12

13 Complimentary tatic CMO Full dder V DD V DD X V DD V DD C o 28 Transistors 13

14 Inversion Property F C o F C o 14

15 Minimize Critical Path by Reducing Inverting tages Even cell Odd cell ,0 C o,0 C o,1 C o,2 C o,3 F F F F Exploit Inversion Property 15

16 etter tructure: The Mirror dder V DD V DD V DD "0"-Propagate Kill C o "1"-Propagate Generate 24 transistors 16

17 Mirror dder tick Diagram V DD C o C o GND 17

18 The Mirror dder The NMO and PMO chains are completely symmetrical. maximum of two series transistors can be observed in the carrygeneration circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node C o. The reduction of the diffusion capacitances is particularly important. The capacitance at node C o is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. The transistors connected to are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. ll transistors in the sum stage can be minimal size. 18

19 Transmission Gate Full dder P V DD V DD P P um Generation V DD P P P V DD C o Carry Generation etup P 19

20 Manchester Carry Chain V DD P i φ P i V DD C o G i Ci C o G i P i D i φ 20

21 Manchester Carry Chain φ V DD P 0 P 1 P 2 P 3 C 3,0 G 0 G 1 G 2 G 3 φ C 0 C 1 C 2 C 3 21

22 Manchester Carry Chain tick Diagram Propagate/Generate Row V DD P i G i φ P i + 1 G i + 1 φ GND Inverter/um Row 22

23 Carry-ypass dder,0 P 0 G 1 P 0 G 1 P 2 G 2 P 3 G 3 C o,0 C o,1 C o,2 F F F F C o,3 lso called Carry-kip P 0 G 1 P 0 G 1 P 2 G 2 P 3 G 3 P=P o P 1 P 2 P 3,0 C o,0 C o,1 C o,2 F F F F Multiplexer C o,3 Idea: If (P0 and P1 and P2 and P3 = 1) then C o3 = C 0, else kill or generate. 23

24 Carry-ypass dder (cont.) it 0 3 it 4 7 it 8 11 it etup t setup etup t bypass etup etup Carry propagation Carry propagation Carry propagation Carry propagation um um um t sum um M bits t adder = t setup + M tcarry + (N/M-1)t bypass + (M-1)t carry + t sum 24

25 Multipliers 25

26 The inary Multiplication Z M + N 1 X Y Z k 2 k = = = = M 1 i = 0 M 1 i = 0 X i 2 i N 1 j = 0 k = 0 N 1 j = 0 Y j 2 j X i Y j 2 i + j with X Y = = M 1 i = 0 N 1 j = 0 X i 2 i Y j 2 j 26

27 The inary Multiplication + x Multiplicand Multiplier Partial products Result 27

28 The rray Multiplier X 3 X 2 X 1 X 0 Y 0 X 3 X 2 X 1 X 0 Y 1 Z 0 H F F H X 3 X 2 X 1 X 0 Y 2 Z 1 F F F H X3 X 2 X 1 X 0 Y 3 Z 2 F F F H Z 7 Z 6 Z 5 Z 4 Z 3 28

29 The MxN rray Multiplier Critical Path H F F H F F F H Critical Path 1 Critical Path 2 F F F H Critical Path 1 & 2 29

30 Carry-ave Multiplier H H H H H F F F H F F F H F F H Vector Merging dder 30

31 Multiplier Floorplan X 3 X 2 X 1 X 0 Y 0 Y 1 C C C C Z 0 H Multiplier Cell F Multiplier Cell Y 2 C C C C Z 1 Vector Merging Cell Y 3 C C C C Z 2 X and Y signals are broadcasted through the complete array. ( ) C C C C Z 7 Z 6 Z 5 Z 4 Z 3 31

32 hifters 32

33 The inary hifter Right nop Left i i i-1 i-1 it-lice i... 33

34 The arrel hifter 3 3 h h2 1 : Data Wire : Control Wire 0 h3 0 h0 h1 h2 h3 rea Dominated by Wiring 34

35 4x4 barrel shifter h0 h 1 h2 h3 Width barrel ~ 2 p m M uffer 35