Lecture 12: Datapath Functional Units

Transcription

1 Introduction to CMOS VLSI Deign Lecture 2: Datapath Functional Unit David Harri Harvey Mudd College Spring 2004

2 Outline Comparator Shifter Multi-input Adder Multiplier 2: Datapath Functional Unit CMOS VLSI Deign Slide 2

3 Comparator 0 detector: A = detector: A = Equality comparator: A = B Magnitude comparator: A < B 2: Datapath Functional Unit CMOS VLSI Deign Slide 3

4 & 0 Detector detector: N-input AND gate 0 detector: NOT + detector (N-input NOR) A 7 A 6 A 5 A 4 A 3 A 2 allone A 3 A 2 A A 0 allzero A A 0 A 7 A 6 A 5 A 4 A 3 A 2 allone A A 0 2: Datapath Functional Unit CMOS VLSI Deign Slide 4

5 Equality Comparator Check if each bit i equal (XNOR, aka equality gate) detect on bitwie equality B[3] A[3] B[2] A[2] B[] A[] A = B B[0] A[0] 2: Datapath Functional Unit CMOS VLSI Deign Slide 5

6 Magnitude Comparator Compute B-A and look at ign B-A = B + ~A + For unigned number, carry out i ign bit B 3 A B C N A B A 3 B 2 A 2 B Z A = B A B 0 A 0 2: Datapath Functional Unit CMOS VLSI Deign Slide 6

7 Signed v. Unigned For igned number, comparion i harder C: carry out Z: zero (all bit of A-B are 0) N: negative (MSB of reult) V: overflow (input had different ign, output ign B) 2: Datapath Functional Unit CMOS VLSI Deign Slide 7

8 Shifter Logical Shift: Shift number left or right and fill with 0 0 LSR = Arithmetic Shift: 0 LSL = Shift number left or right. Rt hift ign extend Rotate: 0 ASR = 0 ASL = Shift number left or right and fill with lot bit 0 ROR = 0 ROL = 2: Datapath Functional Unit CMOS VLSI Deign Slide 8

9 Funnel Shifter A funnel hifter can do all ix type of hift Select N-bit field Y from 2N-bit input Shift by k bit (0 k < N) 2N- N- 0 B C offet + N- offet Y 2: Datapath Functional Unit CMOS VLSI Deign Slide 0

10 Funnel Shifter Operation Computing N-k require an adder 2: Datapath Functional Unit CMOS VLSI Deign Slide

11 Simplified Funnel Shifter Optimize down to 2N- bit input 2: Datapath Functional Unit CMOS VLSI Deign Slide 6

12 Funnel Shifter Deign N N-input multiplexer Ue -of-n hot elect ignal for hift amount nmos pa tranitor deign (V t drop!) k[:0] left Inverter & Decoder Y 3 Y 2 Z 6 Y Z 5 Y 0 Z 4 Z 3 Z 2 Z Z 0 2: Datapath Functional Unit CMOS VLSI Deign Slide 2

13 Funnel Shifter Deign 2 Log N tage of 2-input muxe No elect decoding needed left k k 0 Z 0 Y 0 Z Y Z 2 Y 2 Z 3 Y 3 Z 4 Z 5 Z 6 2: Datapath Functional Unit CMOS VLSI Deign Slide 22

14 Multi-input Adder Suppoe we want to add k N-bit word Ex: = 2: Datapath Functional Unit CMOS VLSI Deign Slide 23

15 Carry Save Addition A full adder um 3 input and produce 2 output Carry output ha twice weight of um output N full adder in parallel are called carry ave adder Produce N um and N carry out X 4 Y 4 Z 4 X 3 Y 3 Z 3 X 2 Y 2 Z 2 X Y Z C 4 S 4 C 3 S 3 C 2 S 2 C S X N... Y N... Z N... n-bit CSA C N... S N... 2: Datapath Functional Unit CMOS VLSI Deign Slide 26

16 CSA Application Ue k-2 tage of CSA Keep reult in carry-ave redundant form Final CPA compute actual reult bit CSA 00_ 0 5-bit CSA _ 00_ X Y Z S C X Y Z S C A B S 2: Datapath Functional Unit CMOS VLSI Deign Slide 27

17 Multiplication Example: 00 : : 5 0 2: Datapath Functional Unit CMOS VLSI Deign Slide 30

18 General Form Multiplicand: Y = (y M-, y M-2,, y, y 0 ) Multiplier: X = (x N-, x N-2,, x, x 0 ) Product: P = y x = xy M N N M j 2 i i j j i2 + i j2 j= 0 i= 0 i= 0 j= 0 y 5 y 4 y 3 y 2 y y 0 x 5 x 4 x 3 x 2 x x 0 multiplicand multiplier x 0 y 5 x 0 y 4 x 0 y 3 x 0 y 2 x 0 y x 0 y 0 p x y 5 x y 4 x y 3 x y 2 x y x y 0 x 2 y 5 x 2 y 4 x 2 y 3 x 2 y 2 x 2 y x 2 y 0 x 3 y 5 x 3 y 4 x 3 y 3 x 3 y 2 x 3 y x 3 y 0 x 4 y 5 x 4 y 4 x 4 y 3 x 4 y 2 x 4 y x 4 y 0 x 5 y 5 x 5 y 4 x 5 y 3 x 5 y 2 x 5 y x 5 y 0 p0 p 0 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p partial product product 2: Datapath Functional Unit CMOS VLSI Deign Slide 37

19 Dot Diagram Each dot repreent a bit x 0 partial product multiplier x x 5 2: Datapath Functional Unit CMOS VLSI Deign Slide 38

20 Array Multiplier y 3 y 2 y y 0 x 0 x CSA Array x 2 x 3 CPA p 7 p 6 p 5 p 4 p 3 p 2 p p 0 Sin A Cin A B critical path A B A B B Cout Sout = Cout Sin Cin Sout Cout Sout Cin = Cout Sout Cin 2: Datapath Functional Unit CMOS VLSI Deign Slide 39

21 Rectangular Array Squah array to fit rectangular floorplan y 3 y 2 y y 0 x 0 x p 0 x 2 p x 3 p 2 p 3 p 7 p 6 p 5 p 4 2: Datapath Functional Unit CMOS VLSI Deign Slide 40

22 Fewer Partial Product Array multiplier require N partial product If we looked at group of r bit, we could form N/r partial product. Fater and maller? Called radix-2 r encoding Ex: r = 2: look at pair of bit Form partial product of 0, Y, 2Y, 3Y Firt three are eay, but 3Y require adder 2: Datapath Functional Unit CMOS VLSI Deign Slide 4

23 Booth Encoding Intead of 3Y, try Y, then increment next partial product to add 4Y Similarly, for 2Y, try 2Y + 4Y in next partial product 2: Datapath Functional Unit CMOS VLSI Deign Slide 42

24 Booth Hardware Booth encoder generate control line for each PP Booth elector chooe PP bit y j y j- X i x 2i- x 2i 2X i M i Booth Encoder x 2i+ Booth Selector PP ij 2: Datapath Functional Unit CMOS VLSI Deign Slide 50

25 Sign Extenion Partial product can be negative Require ign extenion, which i cumberome High fanout on mot ignificant bit 0 PP 0 PP PP 2 PP 3 PP 4 x - x 0 multiplier x PP 5 PP 6 PP 7 PP x 5 x 6 x 7 2: Datapath Functional Unit CMOS VLSI Deign Slide 5

26 2: Datapath Functional Unit Slide 52 CMOS VLSI Deign Simplified Sign Ext. Sign bit are either all 0 or all Note that all 0 i all + in proper column Ue thi to reduce loading on MSB PP 0 PP PP 2 PP 3 PP 4 PP 5 PP 6 PP 7 PP 8

27 Even Simpler Sign Ext. No need to add all the in hardware Precompute the anwer! PP 0 PP PP 2 PP 3 PP 4 PP 5 PP 6 PP 7 PP 8 2: Datapath Functional Unit CMOS VLSI Deign Slide 53

28 Advanced Multiplication Signed v. unigned input Higher radix Booth encoding Array v. tree CSA network 2: Datapath Functional Unit CMOS VLSI Deign Slide 54