Lecture 12: Datapath Functional Units
|
|
- Tiffany Washington
- 5 years ago
- Views:
Transcription
1 Introduction to CMOS VLSI Deign Lecture 2: Datapath Functional Unit David Harri Harvey Mudd College Spring 2004
2 Outline Comparator Shifter Multi-input Adder Multiplier 2: Datapath Functional Unit CMOS VLSI Deign Slide 2
3 Comparator 0 detector: A = detector: A = Equality comparator: A = B Magnitude comparator: A < B 2: Datapath Functional Unit CMOS VLSI Deign Slide 3
4 & 0 Detector detector: N-input AND gate 0 detector: NOT + detector (N-input NOR) A 7 A 6 A 5 A 4 A 3 A 2 allone A 3 A 2 A A 0 allzero A A 0 A 7 A 6 A 5 A 4 A 3 A 2 allone A A 0 2: Datapath Functional Unit CMOS VLSI Deign Slide 4
5 Equality Comparator Check if each bit i equal (XNOR, aka equality gate) detect on bitwie equality B[3] A[3] B[2] A[2] B[] A[] A = B B[0] A[0] 2: Datapath Functional Unit CMOS VLSI Deign Slide 5
6 Magnitude Comparator Compute B-A and look at ign B-A = B + ~A + For unigned number, carry out i ign bit B 3 A B C N A B A 3 B 2 A 2 B Z A = B A B 0 A 0 2: Datapath Functional Unit CMOS VLSI Deign Slide 6
7 Signed v. Unigned For igned number, comparion i harder C: carry out Z: zero (all bit of A-B are 0) N: negative (MSB of reult) V: overflow (input had different ign, output ign B) 2: Datapath Functional Unit CMOS VLSI Deign Slide 7
8 Shifter Logical Shift: Shift number left or right and fill with 0 0 LSR = Arithmetic Shift: 0 LSL = Shift number left or right. Rt hift ign extend Rotate: 0 ASR = 0 ASL = Shift number left or right and fill with lot bit 0 ROR = 0 ROL = 2: Datapath Functional Unit CMOS VLSI Deign Slide 8
9 Funnel Shifter A funnel hifter can do all ix type of hift Select N-bit field Y from 2N-bit input Shift by k bit (0 k < N) 2N- N- 0 B C offet + N- offet Y 2: Datapath Functional Unit CMOS VLSI Deign Slide 0
10 Funnel Shifter Operation Computing N-k require an adder 2: Datapath Functional Unit CMOS VLSI Deign Slide
11 Simplified Funnel Shifter Optimize down to 2N- bit input 2: Datapath Functional Unit CMOS VLSI Deign Slide 6
12 Funnel Shifter Deign N N-input multiplexer Ue -of-n hot elect ignal for hift amount nmos pa tranitor deign (V t drop!) k[:0] left Inverter & Decoder Y 3 Y 2 Z 6 Y Z 5 Y 0 Z 4 Z 3 Z 2 Z Z 0 2: Datapath Functional Unit CMOS VLSI Deign Slide 2
13 Funnel Shifter Deign 2 Log N tage of 2-input muxe No elect decoding needed left k k 0 Z 0 Y 0 Z Y Z 2 Y 2 Z 3 Y 3 Z 4 Z 5 Z 6 2: Datapath Functional Unit CMOS VLSI Deign Slide 22
14 Multi-input Adder Suppoe we want to add k N-bit word Ex: = 2: Datapath Functional Unit CMOS VLSI Deign Slide 23
15 Carry Save Addition A full adder um 3 input and produce 2 output Carry output ha twice weight of um output N full adder in parallel are called carry ave adder Produce N um and N carry out X 4 Y 4 Z 4 X 3 Y 3 Z 3 X 2 Y 2 Z 2 X Y Z C 4 S 4 C 3 S 3 C 2 S 2 C S X N... Y N... Z N... n-bit CSA C N... S N... 2: Datapath Functional Unit CMOS VLSI Deign Slide 26
16 CSA Application Ue k-2 tage of CSA Keep reult in carry-ave redundant form Final CPA compute actual reult bit CSA 00_ 0 5-bit CSA _ 00_ X Y Z S C X Y Z S C A B S 2: Datapath Functional Unit CMOS VLSI Deign Slide 27
17 Multiplication Example: 00 : : 5 0 2: Datapath Functional Unit CMOS VLSI Deign Slide 30
18 General Form Multiplicand: Y = (y M-, y M-2,, y, y 0 ) Multiplier: X = (x N-, x N-2,, x, x 0 ) Product: P = y x = xy M N N M j 2 i i j j i2 + i j2 j= 0 i= 0 i= 0 j= 0 y 5 y 4 y 3 y 2 y y 0 x 5 x 4 x 3 x 2 x x 0 multiplicand multiplier x 0 y 5 x 0 y 4 x 0 y 3 x 0 y 2 x 0 y x 0 y 0 p x y 5 x y 4 x y 3 x y 2 x y x y 0 x 2 y 5 x 2 y 4 x 2 y 3 x 2 y 2 x 2 y x 2 y 0 x 3 y 5 x 3 y 4 x 3 y 3 x 3 y 2 x 3 y x 3 y 0 x 4 y 5 x 4 y 4 x 4 y 3 x 4 y 2 x 4 y x 4 y 0 x 5 y 5 x 5 y 4 x 5 y 3 x 5 y 2 x 5 y x 5 y 0 p0 p 0 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p partial product product 2: Datapath Functional Unit CMOS VLSI Deign Slide 37
19 Dot Diagram Each dot repreent a bit x 0 partial product multiplier x x 5 2: Datapath Functional Unit CMOS VLSI Deign Slide 38
20 Array Multiplier y 3 y 2 y y 0 x 0 x CSA Array x 2 x 3 CPA p 7 p 6 p 5 p 4 p 3 p 2 p p 0 Sin A Cin A B critical path A B A B B Cout Sout = Cout Sin Cin Sout Cout Sout Cin = Cout Sout Cin 2: Datapath Functional Unit CMOS VLSI Deign Slide 39
21 Rectangular Array Squah array to fit rectangular floorplan y 3 y 2 y y 0 x 0 x p 0 x 2 p x 3 p 2 p 3 p 7 p 6 p 5 p 4 2: Datapath Functional Unit CMOS VLSI Deign Slide 40
22 Fewer Partial Product Array multiplier require N partial product If we looked at group of r bit, we could form N/r partial product. Fater and maller? Called radix-2 r encoding Ex: r = 2: look at pair of bit Form partial product of 0, Y, 2Y, 3Y Firt three are eay, but 3Y require adder 2: Datapath Functional Unit CMOS VLSI Deign Slide 4
23 Booth Encoding Intead of 3Y, try Y, then increment next partial product to add 4Y Similarly, for 2Y, try 2Y + 4Y in next partial product 2: Datapath Functional Unit CMOS VLSI Deign Slide 42
24 Booth Hardware Booth encoder generate control line for each PP Booth elector chooe PP bit y j y j- X i x 2i- x 2i 2X i M i Booth Encoder x 2i+ Booth Selector PP ij 2: Datapath Functional Unit CMOS VLSI Deign Slide 50
25 Sign Extenion Partial product can be negative Require ign extenion, which i cumberome High fanout on mot ignificant bit 0 PP 0 PP PP 2 PP 3 PP 4 x - x 0 multiplier x PP 5 PP 6 PP 7 PP x 5 x 6 x 7 2: Datapath Functional Unit CMOS VLSI Deign Slide 5
26 2: Datapath Functional Unit Slide 52 CMOS VLSI Deign Simplified Sign Ext. Sign bit are either all 0 or all Note that all 0 i all + in proper column Ue thi to reduce loading on MSB PP 0 PP PP 2 PP 3 PP 4 PP 5 PP 6 PP 7 PP 8
27 Even Simpler Sign Ext. No need to add all the in hardware Precompute the anwer! PP 0 PP PP 2 PP 3 PP 4 PP 5 PP 6 PP 7 PP 8 2: Datapath Functional Unit CMOS VLSI Deign Slide 53
28 Advanced Multiplication Signed v. unigned input Higher radix Booth encoding Array v. tree CSA network 2: Datapath Functional Unit CMOS VLSI Deign Slide 54
Lecture 18: Datapath Functional Units
Lecture 8: Datapath Functional Unit Outline Comparator Shifter Multi-input Adder Multiplier 8: Datapath Functional Unit CMOS VLSI Deign 4th Ed. 2 Comparator 0 detector: A = 00 000 detector: A = Equality
More informationLecture 12: Datapath Functional Units
Lecture 2: Datapath Functional Unit Slide courtey of Deming Chen Slide baed on the initial et from David Harri CMOS VLSI Deign Outline Comparator Shifter Multi-input Adder Multiplier Reading:.3-4;.8-9
More information9. Datapath Design. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017
9. Datapath Design Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 2, 2017 ECE Department, University of Texas at Austin
More informationArithmetic Circuits-2
Arithmetic ircuits-2 Multipliers Array multipliers hifters Barrel shifter Logarithmic shifter EE 261 Krish hakrabarty 1 Binary Multiplication X = Σ X i 2 i i=0 Multiplicand M-1 N-1 Y = Σ Y i 2 i i=0 Multiplier
More informationArithmetic Circuits-2
Arithmetic Circuits-2 Multipliers Array multipliers Shifters Barrel shifter Logarithmic shifter ECE 261 Krish Chakrabarty 1 Binary Multiplication M-1 X = X i 2 i i=0 Multiplicand N-1 Y = Y i 2 i i=0 Multiplier
More informationArithmetic Circuits-2
Arithmetic Circuits-2 Multipliers Array multipliers Shifters Barrel shifter Logarithmic shifter ECE 261 Krish Chakrabarty 1 Binary Multiplication M-1 X = X i 2 i i=0 Multiplicand N-1 Y = Y i 2 i i=0 Multiplier
More informationCS 140 Lecture 14 Standard Combinational Modules
CS 14 Lecture 14 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego Some slides from Harris and Harris 1 Part III. Standard Modules A. Interconnect B. Operators. Adders Multiplier
More informationLecture 8: Sequential Multipliers
Lecture 8: Sequential Multipliers ECE 645 Computer Arithmetic 3/25/08 ECE 645 Computer Arithmetic Lecture Roadmap Sequential Multipliers Unsigned Signed Radix-2 Booth Recoding High-Radix Multiplication
More informationECE429 Introduction to VLSI Design
ECE429 Introduction to VLSI Design Lecture 5: LOGICAL EFFORT Erdal Oruklu Illinois Institute of Technology Some of these slides have been adapted from the slides provided by David Harris, Harvey Mudd College
More informationHardware Design I Chap. 4 Representative combinational logic
Hardware Design I Chap. 4 Representative combinational logic E-mail: shimada@is.naist.jp Already optimized circuits There are many optimized circuits which are well used You can reduce your design workload
More informationWhat s the Deal? MULTIPLICATION. Time to multiply
What s the Deal? MULTIPLICATION Time to multiply Multiplying two numbers requires a multiply Luckily, in binary that s just an AND gate! 0*0=0, 0*1=0, 1*0=0, 1*1=1 Generate a bunch of partial products
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits
Digital Integrated Circuits Design Perspective rithmetic Circuits Reference: Digital Integrated Circuits, 2nd edition, Jan M. Rabaey, nantha Chandrakasan and orivoje Nikolic Disclaimer: slides adapted
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEM ORY INPUT-OUTPUT CONTROL DATAPATH
More informationBit-Sliced Design. EECS 141 F01 Arithmetic Circuits. A Generic Digital Processor. Full-Adder. The Binary Adder
it-liced Design Control EEC 141 F01 rithmetic Circuits Data-In Register dder hifter it 3 it 2 it 1 it 0 Data-Out Tile identical processing elements Generic Digital Processor Full-dder MEMORY Cin Full adder
More informationECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks
ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational
More informationARITHMETIC COMBINATIONAL MODULES AND NETWORKS
ARITHMETIC COMBINATIONAL MODULES AND NETWORKS 1 SPECIFICATION OF ADDER MODULES FOR POSITIVE INTEGERS HALF-ADDER AND FULL-ADDER MODULES CARRY-RIPPLE AND CARRY-LOOKAHEAD ADDER MODULES NETWORKS OF ADDER MODULES
More informationCSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing
CSE4: Components and Design Techniques for Digital Systems Decoders, adders, comparators, multipliers and other ALU elements Tajana Simunic Rosing Mux, Demux Encoder, Decoder 2 Transmission Gate: Mux/Tristate
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 004 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More informationCSE 140 Lecture 11 Standard Combinational Modules. CK Cheng and Diba Mirza CSE Dept. UC San Diego
CSE 4 Lecture Standard Combinational Modules CK Cheng and Diba Mirza CSE Dept. UC San Diego Part III - Standard Combinational Modules (Harris: 2.8, 5) Signal Transport Decoder: Decode address Encoder:
More informationECE 545 Digital System Design with VHDL Lecture 1A. Digital Logic Refresher Part A Combinational Logic Building Blocks
ECE 545 Digital System Design with VHDL Lecture A Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Laws
More informationLecture 8. Sequential Multipliers
Lecture 8 Sequential Multipliers Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 9, Basic Multiplication Scheme Chapter 10, High-Radix Multipliers Chapter
More informationIntroduction to CMOS VLSI Design. Lecture 5: Logical Effort. David Harris. Harvey Mudd College Spring Outline
Introduction to CMOS VLSI Design Lecture 5: Logical Effort David Harris Harve Mudd College Spring 00 Outline Introduction Dela in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages
More informationDigital Integrated Circuits A Design Perspective
rithmetic ircuitsss dapted from hapter 11 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 Generic Digital Processor MEMORY INPUT-OUTPUT ONTROL
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEMORY INPUT-OUTPUT CONTROL DATAPATH
More informationEE141. Lecture 28 Multipliers. Lecture #20. Project Phase 2 Posted. Sign up for one of three project goals today
EE141-pring 2008 igital Integrated ircuits Lecture 28 Multipliers 1 Announcements Project Phase 2 Posted ign up for one of three project goals today Graded Phase 1 and Midterm 2 will be returned next Fr
More informationEECS150 - Digital Design Lecture 24 - Arithmetic Blocks, Part 2 + Shifters
EECS150 - Digital Design Lecture 24 - Arithmetic Blocks, Part 2 + Shifters April 15, 2010 John Wawrzynek 1 Multiplication a 3 a 2 a 1 a 0 Multiplicand b 3 b 2 b 1 b 0 Multiplier X a 3 b 0 a 2 b 0 a 1 b
More informationEECS150. Arithmetic Circuits
EE5 ection 8 Arithmetic ircuits Fall 2 Arithmetic ircuits Excellent Examples of ombinational Logic Design Time vs. pace Trade-offs Doing things fast may require more logic and thus more space Example:
More informationNumber System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary
Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 00 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More informationDesign of Sequential Circuits
Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing
More informationDIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COMBINATIONAL LOGIC DESIGN: ARITHMETICS (THROUGH EXAMPLES) 2016/2017 COMBINATIONAL LOGIC DESIGN:
More informationDesign at the Register Transfer Level
Week-7 Design at the Register Transfer Level Algorithmic State Machines Algorithmic State Machine (ASM) q Our design methodologies do not scale well to real-world problems. q 232 - Logic Design / Algorithmic
More informationVLSI Arithmetic. Lecture 9: Carry-Save and Multi-Operand Addition. Prof. Vojin G. Oklobdzija University of California
VLSI Arithmetic Lecture 9: Carry-Save and Multi-Operand Addition Prof. Vojin G. Oklobdzija University of California http://www.ece.ucdavis.edu/acsel Carry-Save Addition* *from Parhami 2 June 18, 2003 Carry-Save
More informationAdder Circuits Ivor Page 1
Adder Circuit Adder Circuit Ivor Page 4. The Ripple Carr Adder The ripple carr adder i probabl the implet parallel binar adder. It i made up of k full-adder tage, where each full-adder can be convenientl
More informationEE 447 VLSI Design. Lecture 5: Logical Effort
EE 447 VLSI Design Lecture 5: Logical Effort Outline Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary EE 4475: VLSI Logical Design Effort
More informationLecture 6: Logical Effort
Lecture 6: Logical Effort Outline Logical Effort Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary Introduction Chip designers face a bewildering array
More informationELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378: Digital Logic and Microprocessor Design Winter 2015.
LCTRICAL AND COMPUTR NGINRING DPARTMNT, OAKLAND UNIVRSITY C-378: Digital Logic and Microproceor Deign Winter 5 Note - Unit 7 INTRODUCTION TO DIGITAL SYSTM DSIGN DIGITAL SYSTM MODL FSM + Datapath Circuit:
More informationLecture 14: Circuit Families
Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Pseudo-nMOS Logic q Dynamic Logic q
More informationTree and Array Multipliers Ivor Page 1
Tree and Array Multipliers 1 Tree and Array Multipliers Ivor Page 1 11.1 Tree Multipliers In Figure 1 seven input operands are combined by a tree of CSAs. The final level of the tree is a carry-completion
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 21: Shifters, Decoders, Muxes
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 21: Shifters, Decoders, Muxes [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN
More informationNEW SELF-CHECKING BOOTH MULTIPLIERS
Int. J. Appl. Math. Comput. Sci., 2008, Vol. 18, No. 3, 319 328 DOI: 10.2478/v10006-008-0029-4 NEW SELF-CHECKING BOOTH MULTIPLIERS MARC HUNGER, DANIEL MARIENFELD Department of Electrical Engineering and
More informationInteger Multipliers 1
Integer Multipliers Multipliers must have circuit in most DS applications variety of multipliers exists that can be chosen based on their performance Serial, Serial/arallel,Shift and dd, rray, ooth, Wallace
More informationCSEE 3827: Fundamentals of Computer Systems. Combinational Circuits
CSEE 3827: Fundamentals of Computer Systems Combinational Circuits Outline (M&K 3., 3.3, 3.6-3.9, 4.-4.2, 4.5, 9.4) Combinational Circuit Design Standard combinational circuits enabler decoder encoder
More informationLogic and Computer Design Fundamentals. Chapter 8 Sequencing and Control
Logic and Computer Design Fundamentals Chapter 8 Sequencing and Control Datapath and Control Datapath - performs data transfer and processing operations Control Unit - Determines enabling and sequencing
More information1 Short adders. t total_ripple8 = t first + 6*t middle + t last = 4t p + 6*2t p + 2t p = 18t p
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Study Homework: Arithmetic NTU IC54CA (Fall 2004) SOLUTIONS Short adders A The delay of the ripple
More informationLecture 9: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 9: Combinational Circuits David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q ubble Pushing q Compound Gates
More informationChapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>
Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building
More informationLecture 2: Computer Arithmetic: Adders
CMU 8-447 S 9 L2-29 8-447 Leture 2: Computer Arithmeti: Adder Jame C. Hoe Dept of ECE, CMU January 4, 29 Announement: No la on Monday Verilog Refreher next Wedneday Review P&H Ch 3 Handout: Lab and HW
More informationELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Winter Notes - Unit 7 DATAPATH CIRCUIT
Note - Unit 7 INTRODUCTION TO DIGITL SYSTM DSIGN DIGITL SYSTM MODL FSM + Datapath Circuit: DTPTH CIRCUIT Input FINIT STT MCHIN CONTROL CIRCUIT Output XMPL: CR LOT COUNTR photo receptor If = No light received
More informationLecture 4. Adders. Computer Systems Laboratory Stanford University
Lecture 4 Adders Computer Systems Laboratory Stanford University horowitz@stanford.edu Copyright 2006 Mark Horowitz Some figures from High-Performance Microprocessor Design IEEE 1 Overview Readings Today
More informationLecture 8: Logic Effort and Combinational Circuit Design
Lecture 8: Logic Effort and Combinational Circuit Design Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q Logical Effort q Delay in a Logic Gate
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 19: Adder Design [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN 411 L19
More informationDual-Field Arithmetic Unit for GF(p) and GF(2 m ) *
Institute for Applied Information Processing and Communications Graz University of Technology Dual-Field Arithmetic Unit for GF(p) and GF(2 m ) * CHES 2002 Workshop on Cryptographic Hardware and Embedded
More informationTunable Floating-Point for Energy Efficient Accelerators
Tunable Floating-Point for Energy Efficient Accelerators Alberto Nannarelli DTU Compute, Technical University of Denmark 25 th IEEE Symposium on Computer Arithmetic A. Nannarelli (DTU Compute) Tunable
More informationArithmetic Circuits Didn t I learn how to do addition in the second grade? UNC courses aren t what they used to be...
rithmetic Circuits Didn t I learn how to do addition in the second grade? UNC courses aren t what they used to be... + Finally; time to build some serious functional blocks We ll need a lot of boxes The
More informationLecture 2 Review on Digital Logic (Part 1)
Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%
More informationUNSIGNED BINARY NUMBERS DIGITAL ELECTRONICS SYSTEM DESIGN WHAT ABOUT NEGATIVE NUMBERS? BINARY ADDITION 11/9/2018
DIGITAL ELECTRONICS SYSTEM DESIGN LL 2018 PROFS. IRIS BAHAR & ROD BERESFORD NOVEMBER 9, 2018 LECTURE 19: BINARY ADDITION, UNSIGNED BINARY NUMBERS For the binary number b n-1 b n-2 b 1 b 0. b -1 b -2 b
More informationELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: Digital Logic Design Fall Notes - Unit 7 DATAPATH CIRCUIT
LCTRICL ND COMPUTR NGINRING DPRTMNT, OKLND UNIVRSITY C-7: Digital Logic Deign Fall 7 Note - Unit 7 INTRODUCTION TO DIGITL SYSTM DSIGN DIGITL SYSTM MODL FSM + Datapath Circuit: DTPTH CIRCUIT Input reetn
More informationSlides for Lecture 19
Slides for Lecture 19 ENEL 353: Digital Circuits Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 23 October, 2013 ENEL 353
More informationHardware Implementation of Canonic Signed Digit Recoding
IOSR Journal of VLSI and Signal Proceing (IOSR-JVSP) Volume 6, Iue 2, Ver. I (Mar. -Apr. 2016), PP 11-15 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iorjournal.org Hardware Implementation of Canonic
More informationHomework 4 due today Quiz #4 today In class (80min) final exam on April 29 Project reports due on May 4. Project presentations May 5, 1-4pm
EE241 - Spring 2010 Advanced Digital Integrated Circuits Lecture 25: Digital Arithmetic Adders Announcements Homework 4 due today Quiz #4 today In class (80min) final exam on April 29 Project reports due
More informationEE141- Spring 2004 Digital Integrated Circuits
EE141- pring 2004 Digital Integrated ircuits Lecture 19 Dynamic Logic - Adders (that is wrap-up) 1 Administrative tuff Hw 6 due on Th No lab this week Midterm 2 next week Project 2 to be launched week
More informationVLSI Design, Fall Logical Effort. Jacob Abraham
6. Logical Effort 6. Logical Effort Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 207 September 20, 207 ECE Department, University of
More informationLogical Effort: Designing for Speed on the Back of an Envelope David Harris Harvey Mudd College Claremont, CA
Logical Effort: Designing for Speed on the Back of an Envelope David Harris David_Harris@hmc.edu Harvey Mudd College Claremont, CA Outline o Introduction o Delay in a Logic Gate o Multi-stage Logic Networks
More informationLogic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits
Logic and Computer Design Fundamentals Chapter 5 Arithmetic Functions and Circuits Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance
More informationALUs and Data Paths. Subtitle: How to design the data path of a processor. 1/8/ L3 Data Path Design Copyright Joanne DeGroat, ECE, OSU 1
ALUs and Data Paths Subtitle: How to design the data path of a processor. Copyright 2006 - Joanne DeGroat, ECE, OSU 1 Lecture overview General Data Path of a multifunction ALU Copyright 2006 - Joanne DeGroat,
More informationPart II Addition / Subtraction
Part II Addition / Subtraction Parts Chapters I. Number Representation 1. 2. 3. 4. Numbers and Arithmetic Representing Signed Numbers Redundant Number Systems Residue Number Systems Elementary Operations
More informationPart II Addition / Subtraction
Part II Addition / Subtraction Parts Chapters I. Number Representation 1. 2. 3. 4. Numbers and Arithmetic Representing Signed Numbers Redundant Number Systems Residue Number Systems Elementary Operations
More informationCombinatorial RTL Components
Principles Of Digital Design Combinatorial RTL Components Computation and Reorganization Arithmetic and Comparison Components Logic Components election Components ncoding/decoding Components Bit manipulation
More informationNumbers & Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See: P&H Chapter , 3.2, C.5 C.
Numbers & Arithmetic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See: P&H Chapter 2.4-2.6, 3.2, C.5 C.6 Example: Big Picture Computer System Organization and Programming
More informationLogic Design. CS 270: Mathematical Foundations of Computer Science Jeremy Johnson
Logic Deign CS 270: Mathematical Foundation of Computer Science Jeremy Johnon Logic Deign Objective: To provide an important application of propoitional logic to the deign and implification of logic circuit.
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
More informationChapter 5 Arithmetic Circuits
Chapter 5 Arithmetic Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 11, 2016 Table of Contents 1 Iterative Designs 2 Adders 3 High-Speed
More informationComputer Architecture. ESE 345 Computer Architecture. Design Process. CA: Design process
Computer Architecture ESE 345 Computer Architecture Design Process 1 The Design Process "To Design Is To Represent" Design activity yields description/representation of an object -- Traditional craftsman
More informationA Study on Simulating Convolutional Codes and Turbo Codes
A Study on Simulating Convolutional Code and Turbo Code Final Report By Daniel Chang July 27, 2001 Advior: Dr. P. Kinman Executive Summary Thi project include the deign of imulation of everal convolutional
More informationCombinational Logic Design Arithmetic Functions and Circuits
Combinational Logic Design Arithmetic Functions and Circuits Overview Binary Addition Half Adder Full Adder Ripple Carry Adder Carry Look-ahead Adder Binary Subtraction Binary Subtractor Binary Adder-Subtractor
More informationEECS150 - Digital Design Lecture 11 - Shifters & Counters. Register Summary
EECS50 - Digital Design Lecture - Shifters & Counters February 24, 2003 John Wawrzynek Spring 2005 EECS50 - Lec-counters Page Register Summary All registers (this semester) based on Flip-flops: q 3 q 2
More information3. Combinational Circuit Design
CSEE 3827: Fundamentals of Computer Systems, Spring 2 3. Combinational Circuit Design Prof. Martha Kim (martha@cs.columbia.edu) Web: http://www.cs.columbia.edu/~martha/courses/3827/sp/ Outline (H&H 2.8,
More informationIntroduction to Digital Logic Missouri S&T University CPE 2210 Subtractors
Introduction to Digital Logic Missouri S&T University CPE 2210 Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and Technology cetinkayae@mst.edu
More informationAdditional Gates COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals
Additional Gates COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Additional Gates and Symbols Universality of NAND and NOR gates NAND-NAND
More informationFundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
More information課程名稱 : 數位邏輯設計 P-1/ /6/11
課程名稱 : 數位邏輯設計 P-1/55 2012/6/11 Textbook: Digital Design, 4 th. Edition M. Morris Mano and Michael D. Ciletti Prentice-Hall, Inc. 教師 : 蘇慶龍 INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter
More informationReview for Final Exam
CSE140: Components and Design Techniques for Digital Systems Review for Final Exam Mohsen Imani CAPE Please submit your evaluations!!!! RTL design Use the RTL design process to design a system that has
More informationSpiral 2-1. Datapath Components: Counters Adders Design Example: Crosswalk Controller
2-. piral 2- Datapath Components: Counters s Design Example: Crosswalk Controller 2-.2 piral Content Mapping piral Theory Combinational Design equential Design ystem Level Design Implementation and Tools
More informationLecture 8: Combinational Circuit Design
Lecture 8: Combinational Circuit Design Mark McDermott Electrical and Computer Engineering The University of Texas at ustin 9/5/8 Verilog to Gates module mux(input s, d0, d, output y); assign y = s? d
More informationEE141-Fall 2010 Digital Integrated Circuits. Announcements. An Intel Microprocessor. Bit-Sliced Design. Class Material. Last lecture.
EE4-Fall 2 Digital Integrated ircuits dders Lecture 2 dders 4 4 nnouncements Midterm 2: Thurs. Nov. 4 th, 6:3-8:pm Exam starts at 6:3pm sharp Review session: Wed., Nov. 3 rd, 6pm n Intel Microprocessor
More informationCombinational Logic. By : Ali Mustafa
Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output
More informationUNIT II COMBINATIONAL CIRCUITS:
UNIT II COMBINATIONAL CIRCUITS: INTRODUCTION: The digital system consists of two types of circuits, namely (i) (ii) Combinational circuits Sequential circuits Combinational circuit consists of logic gates
More informationGalois Field Algebra and RAID6. By David Jacob
Galois Field Algebra and RAID6 By David Jacob 1 Overview Galois Field Definitions Addition/Subtraction Multiplication Division Hardware Implementation RAID6 Definitions Encoding Error Detection Error Correction
More informationECE 250 / CPS 250 Computer Architecture. Basics of Logic Design Boolean Algebra, Logic Gates
ECE 250 / CPS 250 Computer Architecture Basics of Logic Design Boolean Algebra, Logic Gates Benjamin Lee Slides based on those from Andrew Hilton (Duke), Alvy Lebeck (Duke) Benjamin Lee (Duke), and Amir
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND
More informationThis Unit: Arithmetic. CIS 371 Computer Organization and Design. Pre-Class Exercise. Readings
This Unit: Arithmetic CI 371 Computer Organization and Design Unit 3: Arithmetic Based on slides by Prof. Amir Roth & Prof. Milo Martin App App App ystem software Mem CPU I/O A little review Binary + 2s
More informationECE 2300 Digital Logic & Computer Organization
ECE 23 Digital Logic & Computer Organization Spring 28 Combinational Building Blocks Lecture 5: Announcements Lab 2 prelab due tomorrow HW due Friday HW 2 to be posted on Thursday Lecture 4 to be replayed
More informationA B OUT_0 OUT_1 OUT_2 OUT_
A B OUT_0 OUT_1 OUT_2 OUT_3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 A Decoder is something that does the opposite of encoding; it converts the data back into its original form. This decoder converts
More informationEECS150 - Digital Design Lecture 10 - Combinational Logic Circuits Part 1
EECS5 - Digital Design Lecture - Combinational Logic Circuits Part Feburary 26, 22 John Wawrzynek Spring 22 EECS5 - Lec-cl Page Combinational Logic (CL) Defined y i = f i (x,...., xn-), where x, y are
More informationClass Website:
ECE 20B, Winter 2003 Introduction to Electrical Engineering, II LECTURE NOTES #5 Instructor: Andrew B. Kahng (lecture) Email: abk@ece.ucsd.edu Telephone: 858-822-4884 office, 858-353-0550 cell Office:
More informationVLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1
VLSI Design Adder Design [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1 Major Components of a Computer Processor Devices Control Memory Input Datapath
More informationELEN Electronique numérique
ELEN0040 - Electronique numérique Patricia ROUSSEAUX Année académique 2014-2015 CHAPITRE 3 Combinational Logic Circuits ELEN0040 3-4 1 Combinational Functional Blocks 1.1 Rudimentary Functions 1.2 Functions
More information