The Design Procedure. Output Equation Determination - Derive output equations from the state table

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Dwain Powers
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1 The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flipflop types and derive flip-flop equations from the state table Output Equation Determination - Derive output equations from the state table Optimization - Optimize the equations Technology Mapping - Find circuit from equations and map to flip-flops and gate technology Verification - Verify correctness of final design

2 Formulation: Finding a State Diagram In specifying a circuit, we use states to remember meaningful properties of past input sequences that are essential to predicting future output values. A SEQUENCE RECOGNIZER is a sequential circuit that produces a distinct output value whenever a prescribed pattern of input symbols occur in sequence, i.e, recognizes an input sequence occurence. We will develop a procedure specific to sequence recognizers to convert a problem statement into a state diagram. Next, the state diagram, will be converted to a state table from which the circuit will be designed.

3 Sequence Recognizer Procedure To develop a sequence recognizer state diagram: Begin in an initial state in which NONE of the initial portion of the sequence has occurred (typically reset state). Add a state that recognizes that the first symbol has occurred. Add states that recognize each successive symbol occurring. The final state represents the input sequence occurrence (feasibly less the final input value). Add state transition arcs which specify what happens when a symbol not in the proper sequence has occurred considering transition to states that represent an input subsequence that has occurred. The last step is required because the circuit must recognize the input sequence regardless of where it occurs within the overall sequence applied since reset.

4 State Assignment Each of the m states must be assigned a unique code Minimum number of bits required is n such that n log 2 m where x is the smallest integer x There are useful state assignments that use more than the minimum number of bits There are 2 n - m unused states

5 Sequence Recognizer Example - Formulation Example: Recognize the sequence Note that the sequence contains and "" is a proper sub-sequence of the sequence. Thus, the sequential machine must remember that the first two one's have occurred as it receives another symbol. Also, the sequence contains as both an initial subsequence and a final subsequence with some overlap, i. e., or. And, the in the middle,, is in both subsequences. The sequence must be recognized each time it occurs in the input sequence.

6 State Diagram: Recognize Define states for the sequence to be recognized: assuming it starts with the arrival of the first symbol, continues through each symbol in the sequence to be recognized, and uses output to mean the full sequence has occurred, with output otherwise. Starting in the initial state (Arbitrarily named "A"): / Add a state that A B recognizes the first symbol: "" State "A" is the initial state, and state "B" is the state which represents the fact that the "first" one in the input subsequence has occurred. The output symbol "" means that the full recognized sequence has not yet occurred.

7 Example: Recognize (continued) After one more, we have: C is the state obtained when the input sequence has two ""s. A / B / C Finally, after and a, we have: A / B / / C D / Transition arcs are used to denote the output function (Mealy Model) Output on the arc from D means the sequence has been recognized To what state should the arc from state D go? Remember:? Note that D is the last state but the output occurs for the input applied in D. This is the case when a Mealy model is assumed.

8 Example: Recognize (continued) A / B / / C D / Clearly the final in the recognized sequence can be in a 2 nd sub-sequence of, and it follows a which cannot belong to the 2 nd sub-sequence. Thus this should represent the same state reached from the initial state after a first is observed. So we obtain: A / B / / C D /

9 Example: Recognize (continued) A / B / C / D / The state have the following abstract meanings: A: No proper sub-sequence of the sequence has occurred. B: The sub-sequence has occurred. C: The sub-sequence has occurred. D: The sub-sequence has occurred. The / on the arc from D to B means that the last has occurred and thus, the sequence is recognized.

10 Example: Recognize (continued) The other arcs are added to each state for inputs not yet listed. Which arcs are missing? A / B / C / D Answer: / "" arc from A "" arc from B "" arc from C "" arc from D.

11 Example: Recognize (continued) State transition arcs must represent the fact that an input subsequence has occurred. Thus we get: / / A / / B C / D / / / Note that the arc from state C to state C implies that State C means two or more 's have occurred.

12 Formulation: Find State Table From the State Diagram, we can fill in the State Table. There are 4 states, one input, and one output. We will choose the form with four rows, one for each current state. From State A, the and input transitions have been filled in along with the outputs. A / / Present State A B C D / B / / C / Next State x= x= / / D Output x= x= A B

13 Formulation: Find State Table From the state diagram, we complete the state table. / / A / B / C / D / / Present Next State Output State x= x= x= x= A A B B A C C D C D A B / What would the state diagram and state table look like for the Moore model?

14 Example: Moore Model for Sequence For the Moore Model, outputs are associated with states. We need to add a state E with output value for the final in the recognized input sequence. This new state E, though similar to B, would generate an output of and thus be different from B. The Moore model for a sequence recognizer usually has more states than the Mealy model.

15 Example: Moore Model (continued) We mark outputs on states for Moore model Arcs now show only state transitions Add a new state E to produce the output A/ B/ C/ D/ E/ Note that the new state, E produces the same behavior in the future as state B. But it gives a different output at the present time. Thus these states do represent a different abstraction of the input history.

16 Example: Moore Model (continued) The state table is shown below Memory aid re-more state in the Moore model: Moore is More. A/ B/ C/ D/ E/ Present State Next State x= x= Output y A A B B A C C D C D A E E A C

17 State Assignment Example Present Next State Output State x= x= x= x= A A B B A B How may assignments of codes with a minimum number of bits? Two A =, B = or A =, B = Does it make a difference? Only in variable inversion, so small, if any.

18 State Assignment Example 2 Present State Next State x= x= Output x= x= A A B B A C C D C D A B How may assignments of codes with a minimum number of bits? = 24 Does code assignment make a difference in cost?

19 Find Flip-Flop Input and Output Equations: Example 2 Counting Order Assignment Assume D flip-flops Interchange the bottom two rows Y Y 2 of the state table, to obtain K-maps for D, D2, and Z: X X Y Y 2 Y Y 2 Y X X Present State Y 2 Y Y 2 Y Next State x = x = D D 2 Z X X Output x = x = Y 2

20 Optimization: Example 2: Counting Order Assignment Performing two-level optimization: X Y Y 2 X X Y Y 2 X Y Y 2 X X Y Y 2 Y Y 2 D D 2 Z Y Y 2 D = Y Y 2 + XY Y 2 D 2 = XY Y 2 + XY Y 2 + XY Y 2 Z = XY Y 2 Gate Input Cost = 22

21 Find Flip-Flop Input and Output Equations: Example 2 Gray Code Assignment Gray Code Assignment: A =, B =, C =, D = The resulting coded state table: Present Next State Output State x= x= x= x= A A B B A C C D C D A B Present State Next State x = x = Output x = x =

22 Find Flip-Flop Input and Output Equations: Example 2 Gray Code Assignment Assume D flip-flops Obtain K-maps for D, D 2, and Z: Present State Next State x = x = Output x = x = Y 2 Y X X Y 2 Y X X Y 2 Y X X Y Y Y Y 2 Y 2 Y 2 D 2 D Z

23 Optimization: Example 2: Assignment 2 Performing two-level optimization: X Y 2 Y Y 2 X X Y D 2 Y 2 X D Y 2 Y X Z Y Y 2 Y Y 2 D 2 = Y 2 Y + XY Gate Input Cost = 9 D = X Select this state assignment to Z = XY 2 Y complete design in slide X Y

24 Map Technology D 2 = Y 2 Y + XY D = X Z = XY 2 Y Library: D Flip-flops with Reset (not inverted) NAND gates with up to 4 inputs and inverters X Clock D D C R C R Y 2 Y Z Reset

25 Mapped Circuit - Final Result D Y C R Z X D Y 2 Clock Reset C R

26 One Flip-flop per State (One-Hot) Assignment Example codes for four states: (Y 3, Y 2, Y, Y ) =,,, and. In equations, need to include only the variable that is for the state, e. g., state with code, is represented in equations by Y instead of Y 3 Y 2 Y Y because all codes with or two or more s have don t care next state values. Provides simplified analysis and design Combinational logic may be simpler, but flip-flop cost higher may or may not be lower cost

27 State Assignment Example 2 (continued) One-Hot Assignment : A =, B =, C =, D =. Present Next State Output State x= x= x= x= A A B B A C C D C D A B The resulting coded state table: Y Y Y 2 Y 3 Present State Next State x = x = Output x = x = D 3 D 2 D D D 3 D 2 D D Z

28 Find Flip-Flop Input and Output Equations: Example 2: One Hot Assignment Equations read from next state variable entries in table: D = X(Y + Y + Y 3 ) or X Y 2 D = X(Y + Y 3 ) D 2 = X(Y + Y 2 ) or X(Y + Y 3 ) D 3 = X Y 2 Z = XY 3 Gate Input Cost = 4 Combinational cost intermediate plus cost of two more flip-flops needed.

29 Sequential Design: Example 3 Design a sequential modulo 3 accumulator for 2-bit operands Definitions: Accumulator - a circuit that accumulates the sum of its input operands over time - it adds each input operand to the stored sum, which is initially. Modulo n adder - an adder that gives the result of the addition as the remainder of the sum divided by n Example: modulo 3 = remainder of 4/3 = Stored sum: (Y,Y ), Input: (X,X ), Output: (Z,Z )

30 Example 3 (continued) Complete the state diagram: Reset A/ C/ B/

31 Example 3 (continued) Complete the state table X X Z Z Y Y A () X B () X - () X X X X C () X Codes are in gray code order to ease use of K-maps in the next step

32 Example 3 (continued) Find optimized flip-flop input equations for D flip-flops X X X X Y Y D X Y Y Y X X X X X X X X Y X X Y X X X X X D Y X X D = Y X + Y Y X + Y X X D = Y X + Y Y X + Y X X

33 Circuit - Final Result with AND, OR, NOT X Y X D Z C R D Y Z Reset Clock C R

34 Design Procedure The procedure for designing synchronous sequential circuits can be summarized by a list of recommended steps:. From the word description and specifications of the desired operation, derive a state diagram for the circuit. 2. Reduce the number of states if necessary. 3. Assign binary values to the states. 4. Obtain the binary-coded state table. 5. Choose the type of flip-flops to be used. 6. Derive the simplified flip-flop input equations and output equations. 7. Draw the logic diagram. 34

35 State diagram for sequence detector A system with one input x and one output z such that z = if x has been at least three consecutive clock times. 35

36 Synthesis Using D Flip-Flops A = D A (A, B, x) = (3, 5, 7) B = D B (A, B, x) = (, 5, 7) y(a, B, x) = (6, 7) 36

37 Synthesis Using D Flip-Flops 37

38 Synthesis Using D Flip-Flops D A = Ax +Bx D B = Ax + Bx y = AB 38

39 Synthesis Using JK Flip-Flops 39

40 Synthesis Using JK Flip-Flops

41 Synthesis using JK Flip-Flops 4

42 Example 5: Design a sequential circuit given below using J-K FlipFlop 42

43 Example 5: TRUTH TABLE I/p Present st. Next state o/p 43

44 Example 5: Design a sequential circuit k 3 =Y y y y j 3 =Y y y x y y y x x y

45 Example 5: Design a sequential circuit k 2 = y y x y j 2 = y y x y y y x y 45

46 Example 5: Design a sequential circuit k =y 3 x+y 3 y y y y y y j =y 3 y 2 x y y y x x y 46

47 Sequential Code Converter BCD-Excess-3 LSB MSB

48 Sequential Code Converter BCD-Excess-3

49 Sequential Code Converter BCD-Excess-3

50 Sequential Code Converter BCD-Excess-3

51 Sequential Code Converter BCD-Excess-3

52 Sequential Code Converter BCD-Excess-3

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Sequential Circuit Design

Sequential Circuit Design Sequential Circuit esign esign Procedure. Specification 2. Formulation Obtain a state diagram or state table 3. State Assignment Assign binary codes to the states 4. Flip-Flop Input Equation etermination