I. Motivation & Examples

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1 I. Motivation & Examples Output depends on current input and past history of inputs. State embodies all the information about the past needed to predict current output based on current input. State variables, one or more bits of information. If the current State of the circuit is known at time t, what is the state of the circuit at time (t+) Answer: the next state depends on current state and input

2 I. Motivation & Examples Describing sequential circuit State table For each current-state, specify next-states as function of inputs For each current-state, specify outputs as function of inputs State diagram Graphical version of state table Example : TV channel control Let the channel # represent the state of the circuit Input are up/down on the channel control 2 on u u u u u d d d d d u: up d: down

3 I. Motivation & Examples Example 2: A sequential process that inputs an n-bit binary string and outputs if the string contains an even number of s 0 SLN (final output) 0 SLN 0 (final output) What represents the state of the circuit? Case: State as the number of s read so far (possibly infinite # of states) 3 Case 2: Two states E and O E (even): if the # of s read so far is even O (odd) if the # of s read so far is odd

4 I. Motivation & Examples Example 2: State Diagram for Case Input Output 0 /0 / /0 / /0 / 2n 0/ 0/0 0/ 0/0 0/ 0/ Example 2: State Diagram for Case 2 Input Output 4 E 0/ /0 / O 0/0

5 I. Motivation & Examples Example 2: State Diagram for Case 2 Input Output E 0/ /0 / O 0/0 Better design Has less states 5

6 I. Motivation & Examples Example 3: Discuss sequential n-bits comparator Compare two n-bits numbers X=[Xn-,, X0], Y=[Yn-,, Y0] Output if X>Y Use the basic -bit comparator designed in class Shift right... Xn- Xn-2 Xn-3 X2 X X0 Xi Fi- -bit Comparator Yi Ci Operation controlled by a clock to decide:.when to shift input data.when output Fi is stable Yn- Yn-2 Yn-3... Y2 Y Y0 Shift right Fi 6

7 I. Motivation & Examples Example 4: Discuss sequential n-bits adder Add two n-bits numbers X=[Xn-,, X0], Y=[Yn-,, Y0] Output S=X+Y where [Sn,Sn-,,S0] Use the basic -bit adder with carry in and carry out Shift right... Xn- Xn-2 Xn-3 X2 X X0 Xi Ci- -bit Full adder Ci Yi Operation controlled by a clock to decide:.when to shift input data.when output are ready 7... Shift right Yn- Yn-2 Yn-3 Y2 Y Y0 Sn Ci Shift right... Sn- Sn-2 S2 S S0

8 II. General Representation Clock signals Sequential circuit are controlled by a clock signal Very important with most sequential circuits State variables change state at clock edge. 8

9 II. General Representation General diagram of sequential circuit Sequential circuit are controlled by a clock signal Very important with most sequential circuits State variables change state at clock edge. Input Output i0 i in Current states SLN Next states o0 o om Feedback Memory components 9 State variables: s0,s, sk

10 II. General Representation Some important questions How to represent the states of a sequential circuit? How to memorize the (current and next) states? How to determine the next of the circuit? How to determine the outputs as a function F(state) of current state only? as a function F(input,state) of both input and current state? The concept of STATE is very important 0

11 II. General Representation Memory component How do we represent the states? Memory component are used as state variables Goal: Memorize the current state of the circuit How are memory components implemented? Latch, Flip-flop are -bit memory component

12 Bistable element The simplest sequential circuit Two states One state variable, say, (N or _L the complement of ) HIGH LOW LOW HIGH 2

13 Bistable element The simplest sequential circuit Two states One state variable, say, LOW HIGH HIGH LOW 3

14 Bistable element: Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V 4

15 Bistable element: Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 5

16 Bistable element: Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V VV V V V 6

17 II. General Representation Bistable element: summary 2 7 If (=0), then input to Not gate 2 is 0 ==> Output of Not gate 2 is (_L =) ==> The input of Not gate is, so output of Not gate is 0 ==> Stable output (=0) and (_L = ) If (=), then input to Not gate 2 is ==> Output of Not gate 2 is 0 (_L =0) ==> The input of Not gate is 0, so output Not gate is ==> Stable output (=) and (_L = 0)

18 S-R Latch. How to control it? Screwdriver Control inputs S-R latch Contradiction!!!! 8

19 S-R Latch. 9 Set operation: SR > 0, set the device output to = regardless of current value of Reset operation: SR > 0, set the device output to =0 regardless of current value of Hold operation: SR > 00 or > 00, Device output are the same as last output values Only one input value changes Possible input changes: SR: > 0 ---> > 0 ---> 00. Input SR = is not allowed ( Both NOR gates output 0, i.e = =0 )

20 S-R latch operation 20

21 Propagation delay Minimum pulse width S-R latch timing parameters 2 Progation delay Minimum time to maintain signal at

22 S-R latch symbols 22

23 S-R latch with enable 23

24 Sequential network architecture (revisited) Input i in... SLN... Output o om M... Components Mi are latches/flip flops 24 Mk Operation rules: Memory components Mi must be in stable state before input changes Only one input of the component Mi can change at a time

25 Charcteristics equation of S-R latch Definition: The characteristic equation specifies a flip-flop next state as a function of its current state and inputs 25 Notation: Let q represent the current state of the flip-flop and its next Characteristics table S R q X X =q =0 = Not allowed Hold Reset Set

26 Charcteristics table (other representation) Characteristics table S R 0 0 q =q 0 0 =0 0 = X Not allowed Hold Reset Set 26

27 Charcteristics equation of S-R latch Use the characteristics table to get an excitation map of the flip flop Characteristics table S R q X X =q =0 = SR q X X Use K-map method to derive the characteristics equation: 27 = S + R q

28 Excitation table of SR flip flop The excitation table describes the input values of S and R that cause the corresponding transitions (q ---> ) from current to next state 28 Types of transitions: q ---> 0 ---> > ---> 0 Excitation table of S R latch ---> 0 0 to hold current value OR 0 to set = q ---> S R 0 ---> 0 0 X 0 ---> 0 ---> > X to hold current value OR 0 to reset =0

29 JK Flip- Flop Recall: In SR flip flop, both input S, R cannot be (SR=) This restriction is removed in a JK flip flop. The behavior of the JK flip flop is as follows: 29 Characteristics table J K q =q =0 = = (Toggle) Hold Reset Set

30 Charateristics of JK flip flop (other representation) Characteristics table J K 0 0 q q' =q =0 = = q (Toggle) Hold Reset Set 30 Characteristics table ( Clocked JK flip flop ) C J K q 0 q' 0 x x Disabled =q =0 = = q (Toggle) Hold Reset Set

31 Charcteristics equation of Jk Flip flop Use the characteristics table to get an excitation map of the flip flop Characteristics table J K q =q =0 = = JK q Use K-map method to derive the characteristics equation: 0 3 = Jq + Kq

32 Excitation table of JK flip flop The excitation table describes the input values of S and R that cause the corresponding transitions (q ---> ) from current to next state 32 Types of transitions: q ---> 0 ---> > ---> 0 Excitation table of JK flip flop ---> 0 0 to hold current value OR 0 to set = q ---> J K 0 ---> 0 0 X 0 ---> X ---> 0 X ---> X to hold current value OR 0 to reset =0

33 Excitation table of JK flip flop The excitation table describes the input values of S and R that cause the corresponding transitions (q ---> ) from current to next state 33 Types of transitions: q ---> 0 ---> > ---> 0 Excitation table of JK flip flop ---> 0 0 to hold current value OR 0 to set = q ---> J K 0 ---> 0 0 X 0 ---> X ---> 0 X ---> X to hold current value OR 0 to reset =0

34 JK Flip flop Symbols J J K N K Clocked JK Flip flop J J CK CK K N K N 34

35 D Flip- flop ( Delay flip flop) 35 This flip flop has only one control input. The D flip flop simply retains its input between clock pulses Characteristics table D q =d Characteristics table ( Clocked D flip flop ) C D 0 0 x 0 =d Disabled

36 Charcteristics equation of D Flip flop Use the characteristics table to get an excitation map of the flip flop Characteristics table D q Characteristics equation: = D 36

37 D Flip flop Symbols D D N Clocked JK Flip flop D D CK CK N N 37

38 D latch 38

39 D-latch operation 39

40 D-latch timing parameters Propagation delay (from C or D) Setup time (D before C edge) Hold time (D after C edge) 40

41 Edge-triggered D flip-flop behavior 4

42 Edge-triggered D flip-flop behavior 42

43 D flip-flop timing parameters Propagation delay (from CLK) Setup time (D before CLK) Hold time (D after CLK) 43

44 IV. Counters Definitions A counter is a sequential-circuit that generates a predetermined number sequence over and over again A counter can be used as a digital clock special sequence generator program counter pulse counter 44

45 IV. Counters Examples

46 IV. Counters Types of counters 46 Counters are often implemented by Flip flops. They are synchronous if all flip flops are clocked by the same signal ripple (asynchronous) individual flip flop are clocked at different times Counters may be classified by other characteristics: mod N counter or divide-by- N counter, if counter has N distinct states (State = a number of the counted sequence) by the number of fli flops in the counter: n bit counter Other types of counter: binary up (or down) counter : successive states represent an increasing binary count 00 --> 0 --> 0 --> --> 00.. gray code binary counter 00 --> 0 ---> ---> 0 ---> 00

47 IV. Counters Problem Statement Intuitive Design of a counter Design a sequential device to generate the sequence 0,, 2, 3 over and over again There are 4 distinct states (divide-by-4) counter Encode the four states as follows; 0 encoded by 00 encoded by 0 2 encoded by 0 3 encoded by Represent each binary bit of a code by a flip flop (in this example, let us use JK flip flops to design the counter)

48 00 IV. Counters Intuitive Design of a counter Flip flop 0 changes state at every clock pulse Flip flop changes states every two clock pulses 00 Flip flop Flip flop 0 48 State transition flip flop 0 State transition flip flop 0

49 IV. Counters Intuitive Design of a counter Design using JK flip flops for states 0 and of the counter SS0 : 00 --> 0 --> 0 --> --> 00. S S0 J J CK CK K N K N EN 49

50 IV. Counters Intuitive Design of a 4 bit binary counter Design using JK flip flops S3S2SS0 : > > > 00 --> > 00 --> --> 0000 There are 6 states design requires four flip flops Synchronous design, all flip flops clocked by the same signal S0 Changes state (toggles) every clock pulse S Changes state (toggles) when S0 = S2 Changes state (toggles) when S= and S0 = S3 Changes state (toggles) when S2=, S= and S0= 50

51 IV. Counters Intuitive Design of a 4 bit binary counter Design using JK flip flops J J J J CK CK CK CK K N K N K N K N S3 S2 S S0 EN 5

I. Motivation & Examples

I. Motivation & Examples Output depends on current input and past history of inputs. State embodies all the information about the past needed to predict current output based on current input. State variables,