Verilog HDL:Digital Design and Modeling. Chapter 11. Additional Design Examples. Additional Figures

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1 Chapter Additional Design Examples Verilog HDL:Digital Design and Modeling Chapter Additional Design Examples Additional Figures

2 Chapter Additional Design Examples 2 Page 62 a b y y 2 y 3 c d e f Figure State diagram for a Johnson counter with a nonsequential counting sequence There are two unused states, y y 2 y 3 = and Page 63 y 2 y 3 y 3 2 y 2 y 3 y Dy Dy 2 y 2 y 3 y Dy 3 Figure 2 Input maps for the Johnson counter of Figure using D flip-flops The unused states are y y 2 y 3 = and

3 Chapter Additional Design Examples 3 Page 63 Dy = y 3 ' Dy 2 = y Dy 3 = y 2 () δ Y λ y y 3 +Clock D inst > +y y 2 +y D inst2 > +y 2 y 3 +y 2 D inst3 > +y 3 y3 Logic diagram for the Johnson counter of Figure using D flip- Figure 3 flops

4 Chapter Additional Design Examples 4 Page 67 +clk rst_n clk > CTR3 rst_n inst 2 ctr[2] ctr[] ctr[] inst2 shftr_clk > SRG3 rst_n inst3 2 +ctr[2] +ctr[] +ctr[] +shftr[2] +shftr[] +shftr[] +sngl_ shftr[] shftr[] shftr[2] +dbl_ inst4 inst5 net net2 serial_in inst6 Figure 8 Logic diagram for the counter-shifter

5 Chapter Additional Design Examples 5 Page 6 Table Functions for the Universal Shift Register Function Function Code Shift Amount (right/left) NOP (No operation) Shift right Shift left Load clk rst_n data_in [7:] fctn [:] shift_amt [:] Universal Shift Register q [7:] (a) data_in [7] data_in [] q [7] q [] (b) Figure 4 Universal shift register

6 Chapter Additional Design Examples 6 Page 68 Code word (n bits) Message word (m bits) m, m 2,, m m Parity check word (k bits) p, p 2,, p k Code word X = x, x 2,, x m, x m +,, x n Figure 8 Code word of n bits containing m message bits and k parity check bits Page 62 p, p 2, m 3, p 4, m 5, m 6, m 7, p 8, m 9, m, m, m 2 where m 3, m 5, m 6, m 7, m 9, m, m, m 2 are the message bits and p, p 2, p 4, p 8 are the parity check bits for groups E, E 2, E 4, E 8, respectively, as shown below Group E = p m 3 m 5 m 7 m 9 m Group E 2 = p 2 m 3 m 6 m 7 m m Group E 4 = p 4 m 5 m 6 m 7 m 2 Group E 8 = p 8 m 9 m m m 2

7 Chapter Additional Design Examples 7 Page 622 p p 2 m 3 p 4 m 5 m 6 m 7 Message to be sent Code word sent Code word received Group E = p m 3 m 5 m 7 = = Error = Group E 2 = p 2 m 3 m 6 m 7 = = No error = Group E 4 = p 4 m 5 m 6 m 7 = = Error = Groups E 4 E 2 E Syndrome word

8 Chapter Additional Design Examples 8 Page 623 Table 2 Examples of Single Error Correction and Double Error Detection Code Word Format Syndrome Code Word Parity p p 2 m 3 p 4 m 5 m 6 m 7 p cw E 4 E 2 E Single Error Double Error Sent Received Bad Yes No Sent Received Bad Yes No Sent Received Good No Yes Sent Received Good No Yes Sent Received Bad No No Data bus reg p +p +m 3 2k+ DX p +m 5 2 +m 7 m 3 +p 2 2 Data bus p +m 2k m 6 4 m +m p m m 2k m m 6 7 +m 7 Syndrome word +m 3 +m 5 +m 6 +m 7 Valid data Figure 2 Hamming code error detection and correction

9 Chapter Additional Design Examples 9 Page 625 m3 m5 m7 m9 m task pbit_generate task error_inject p mr3 mr5 mr7 mr9 mr define error bits e_err decoder DX 4:6 error correction logic m3 m6 m7 m m m5 m6 m7 m2 m9 m m m2 p2 mr3 mr6 mr7 mr mr p4 mr5 mr6 mr7 mr2 p8 mr9 mr mr mr2 e2_err e4_err e8_err mr3_err mr3 mr5_err mr5 mr6_err mr6 mr7_err mr7 mr9_err mr9 mr_err mr mr_err mr mr2_err mr2 mv3 mv5 mv6 mv7 mv9 mv mv mv2 e_err e2_err e4_err e8_err Figure 2 Logic diagram for the Hamming code error detection and correction circuit of Examlple 2

10 Chapter Additional Design Examples Page 626 Bit position = Data = m3 m5 m6 m7 m9 m m m2 p p2 p4 p8 The statement error_inject () passes the constant to the task as the bit_number Then the statement bit_position = ' b << bit_number shifts a bit eleven bit positions to the left to location m3 The message bit m3 is exclusive-ored with the bit as shown below, thereby inverting m3 The message containing the error is then passed back to the task invocation as the received message, which is then corrected by the error correction logic In a similar manner, errors are injected into message bits m7, m9, and m2 Data = m3 m5 m6 m7 m9 m m m2 p p2 p4 p8 XOR = Received m3 ' m5 m6 m7 m9 m m m2 p p2 p4 p8 message =

11 Chapter Additional Design Examples Page 63 i + k + i + k i + k i + i i Multiplier k consecutive s In the sequential add-shift method, the multiplicand would be added k times to the shifted partial product The number of additions can be reduced by the following property of binary strings: 2 i + k 2 i = 2 i + k + 2 i + k i i (2) The right-hand side of the equation is a binary string that can be replaced by the difference of two numbers on the left-hand side of the equation Thus, the k consecutive s can be replaced by the following string: i + k + i + k i + k i + i i Multiplier + k consecutive s Addition of the multiplicand Subtraction of the multiplicand

12 Chapter Additional Design Examples 2 Page i + k 2 i i 2 2 Multiplier +3 k = 4 The validity of Equation 2 can be verified using the multiplier of +3 shown above 2 i + k 2 i = 2 i + k = = = 3 Thus, the multiplier (+3) can be regarded as the difference of two numbers: 32 2, as shown below (32) ) (2) (3) The product can be generated by one subtraction in column 2 i and one addition in column 2 i + k, as shown below; that is, by adding 32 and subtracting 2 In this case, adding 2 5 times the multiplicand and subtracting 2 times the multiplicand yields the appropriate result Standard multiplier k = 4 Recoded multiplier + k =3

13 Chapter Additional Design Examples 3 Page 633 Table 3 Booth Multiplier Recoding Table Multiplier Bit i Bit i Version of Multiplicand multiplicand + multiplicand multiplicand multiplicand Standard sequential add-shift Multiplicand +53 Multiplier ) Page 634 Booth algorithm Multiplicand +53 Recoded multiplier ) + +59

14 Chapter Additional Design Examples 4 Page 634 Multiplicand +3 Multiplier ) 2 56 Booth algorithm Multiplicand +3 Recoded multiplier ) Page 634 Multiplicand +5 Multiplier ) Page 635 Booth algorithm Multiplicand +5 Recoded multiplier ) + +45

15 Chapter Additional Design Examples 5 Page 635 Multiplicand 9 Multiplier ) Booth algorithm Multiplicand 9 Recoded multiplier ) Page 635 Multiplicand 3 Multiplier ) 7 +9 Page 636 Booth algorithm Multiplicand 3 Recoded multiplier ) + +9

16 Chapter Additional Design Examples 6 Page 636 Multiplicand +9 Multiplier ) 29 Booth algorithm Multiplicand +9 Recoded multiplier ) Page 637 Multiplicand +7 Multiplier ) a_ext_neg a_ext_pos Booth algorithm Multiplicand +7 Recoded multiplier ) + + pp pp2 pp3 pp4 +35 a_neg

17 Chapter Additional Design Examples 7 Page 642 y y 2 y 3 a x x ' x b ' x ' c x x d z z t t 3 e z 2 z 2 t t Figure 29 State diagram for the Moore machine of Section 6 clk x set_n set2_n set3_n rst_n rst2_n rst3_n Moore structural synchronous sequential machine y[:3] y_n[:3] z z 2 Figure 3 Block diagram for the Moore machine of Section 6

18 Chapter Additional Design Examples 8 Page 643 set_n +clk y 2 +y 3 x y +y 2 +x rst_n inst inst2 net net2 inst3 net3 y S D inst4 > R +y y set2_n +y rst2_n inst5 inst6 net5 net6 inst7 net7 y 2 S D inst8 > R +y 2 y 2 set3_n rst3_n net9 inst9 net inst net inst y 3 S D inst2 > R +y 3 y 3 inst3 +z inst4 +z 2 Figure 3 Logic diagram for the Moore machine of Figure 29

19 Chapter Additional Design Examples 9 Page 65 a y y 2 x 2 x b x x 2 c x 2 x z Figure 36 State diagram for the Mealy pulse-mode machine of Section 7 Page 65 Latches Inputs x x 2 y y y 2 r r 2 3 R y y 2 r S 2 3 R y 2 y y 2 S s 2 3 S y y 2 r R 2 3 r Figure 37 Input maps for the Mealy pulse-mode machine of Figure 36

20 Chapter Additional Design Examples 2 Page 652 set_n +x +x 2 inst net +y 2 +y inst3 net3 inst2 inst4 net2 net4 Ly inst5 inst6 net5 net6 y S D inst7 > R inst +y +z x x 2 rst_n Ly 2 inst8 inst9 net8 net9 y 2 S D inst > R +y 2 Figure 39 Logic diagram for the Mealy pulse-mode machine of Figure 36

21 Chapter Additional Design Examples 2 Page 657 a x y y 2 y 3 x ' z b x ' x c x x ' z Figure 44 State diagram for the Mealy one-hot machine of Section 8

22 Chapter Additional Design Examples 22 Page 658 y 2 y 3 y x x ' Dy = y 3 x + y x ' Dy y 2 y 3 y 3 2 x' x Dy 2 = y x + y 2 x ' Dy 2 y 2 y 3 y x ' 3 2 x Dy 3 = y 2 x + y 3 x ' Dy 3 (a) y 2 y 3 y x x z = y 2 ' x z (b) Figure 45 Figure 44 (a) Input maps and (b) output map for the Mealy one-hot machine of

23 Chapter Additional Design Examples 23 Page 659 set_n_y +clk +y 3 +x +y x rst_n_y inst inst2 net net2 inst3 net3 y S D inst4 > R +y set_n_y y 2 +y 2 inst5 inst6 net5 net6 inst7 net7 y 2 S D inst8 > R +y 2 inst3 +z rst_n_y y 2 net9 inst9 net inst net inst y 3 S D inst2 > R +y 3 Figure 46 Logic diagram for the Mealy one-hot machine of Figure 44

24 Chapter Additional Design Examples 24 Page 665 a x y y 2 y 3 x ' z b x ' x c x x ' z Figure 5 State diagram for a Mealy one-hot sequential machine

25 Chapter Additional Design Examples 25 Page 67 Operand B Operand A Cout Decimal arithmetic element Cin Result Figure 56 Decimal arithmetic element Page ) ) 93 89

26 Chapter Additional Design Examples 26 Page ) 42 +) ) 87 +) (89)

27 Chapter Additional Design Examples 27 Page 674 Table 5 Nines Complementer Subtrahend 9s Complement b 3 b 2 b b f 3 f 2 f f m 9s complementer f [3:] b[3:] Figure 57 Block diagram for a 9s complementer

28 Chapter Additional Design Examples 28 Page 675 f = b m f = b f 2 = m' b 2 + m(b 2 b ) f 3 = m' b 3 + m b 3 ' b 2 ' b ' (6) +b[] +m +b[] inst +f[] +f[] m +b[2] inst2 net2 inst3 net3 inst4 net4 inst5 +f[2] +b[3] b[3] b[2] inst6 inst7 net6 net7 inst8 +f[3] b[] Figure 58 Logic diagram for a 9s complementer

29 Chapter Additional Design Examples 29 Page 68 m a[] a[] a[2] a[3] b[] b[] b[2] b[3] 9s f[] f[] f[2] f[3] inst Adder cin A inst2 2 B 3 cout sum[] sum[] sum[2] sum[3] cout3 Adder cin A inst6 2 3 B cout bcd[] bcd[] bcd[2] bcd[3] inst3 inst4 net3 net4 aux_cy inst5 a[4] a[5] a[6] a[7] b[4] b[5] b[6] b[7] 9s f[4] f[5] f[6] f[7] inst7 Adder cin A inst8 2 B 3 cout sum[4] sum[5] sum[6] sum[7] cout7 Adder cin A inst2 2 3 B cout bcd[4] bcd[5] bcd[6] bcd[7] net9 inst9 inst net inst cout Figure 62 Logic diagram for a BCD adder/subtractor

30 Chapter Additional Design Examples 3 Page 686 Memory data bus A full B full Ibufr A 3 2 Ibufr B 3 2 IPC IPC IPC 2 S S Mux array IR Opcode 3 2 Figure 67 Instruction buffer for 2- and 4-byte instructions

31 Chapter Additional Design Examples 3 Page 687 Ifetch Decode Execute Store Ifetch Decode Execute Store Ifetch Decode Execute Store Ifetch Decode Execute Store Ifetch Decode Execute Store Ifetch Decode Execute Store Ifetch Decode Execute Store Ifetch Decode Execute Store One clock cycle Figure 68 Example of a 4-stage pipeline Iunit Decode Eunit Store Interstage buffers Figure 69 Four stages of a pipeline showing the interstage storage buffers

32 Chapter Additional Design Examples 32 Page 689 Op Code Opnd A Opnd B Dst nnnn RRR RRR RRR where RRR specifies one of eight registers ( 7) for opnd A, opnd B, and Dst Op Code Opnd A Dst (Load) Memory address RRR Op Code Opnd A Dst (Store) RRR Memory address Figure 7 Instruction format for the pipelined RISC processor

33 Chapter Additional Design Examples 33 Page 69 icache iunit decode eunit dcache clk rst_n eu_dcenbl instruction iu_instr eu_rdwr ir decoder ctrl 3 > 3 eu_reg_wr_vld opcode opcode iu_pc du_opcode opcode_out > pc 5 > eu_load_op 4 > + dcaddr dcaddr du_addrin eu_dcaddr > 4 > 4 opnda > 3 opndb du_opndb_addr > du_opnda_addr mux a 3 > alu rslt mux b eu_result 8 dst du_dstin dst eu_dst 3 > 3 > 3 5 dc_dataout clk rst_n regfile regfile:7_out Figure 7 Architecture for the pipelined RISC processor of Section

34 Chapter Additional Design Examples 34 Page 69 risc structural system_top structural risc_cpu_top risc risc risc risc risc risc icache icache_tb iunit iunit_tb decode decode_tb eunit eunit_tb regfile regfile_tb dcache dcache_tb clk rst_n instruction iu_pc structural risc_cpu_top risc risc risc risc iunit iunit_tb decode decode_tb eunit eunit_tb regfile regfile_tb eu_dcenbl eu_dcaddr eu_result eu_rdwr dc_dataout risc structural system_top_tb risc structural system_top clk rst_n risc icache structural risc_cpu_top risc dcache Figure 72 Structural block diagram for the pipelined RISC processor of Section

35 Chapter Additional Design Examples 35 Page 692 Table 7 Instruction Cache Contents Address Operation Op Code Opnd A Opnd B Dst LD Not used LD Not used LD Not used LD Not used LD Not used LD Not used LD Not used LD Not used ADD SUB AND OR XOR INC DEC NOT NEG SHR SHL ROR ROL ST Not used ST Not used ST Not used ST Not used ST Not used ST Not used ST Not used ST Not used NOP NOP NOP

36 Chapter Additional Design Examples 36 Page 693 Table 8 Data Cache Contents SRC DST Address Data Table 9 Register File Contents before Execution Table Register File Contents after Execution Address Data Address Data

37 Chapter Additional Design Examples 37 Page 694 instruction 3 instruction (To iunit) pc 5 risc_pc (From iunit) 3 Figure 73 Instruction cache for the pipelined RISC processor

38 Chapter Additional Design Examples 38 Page 695 clk clk rst_n rst_n instruction ir instruction 3 (From icache) > ir 3 iu_instr (To decode) pc iu_pc (To icache) 5 > pc + Figure 74 Instruction unit for the pipelined RISC processor

39 Chapter Additional Design Examples 39 Page 696 clk rst_n iu_instr 3 (From iunit) instr decoder opcode > opcode dcaddr 4 du_opcode (To eunit) > dcaddr 4 du_dcaddr (To eunit) opnda > opnda 3 du_opnda_addr (To eunit) opndb > opndb 3 du_opndb_addr (To eunit) dst > dst 3 du_dst(to eunit) Figure 75 Decode unit for the pipelined RISC processor

40 Chapter Additional Design Examples 4 Page 697 dcenbl rdwr reg_wr_vld clk rst_n du_opcode (From decode) (From decode) du_addrin regfile:7_out 8 (From regfile) du_opnda_addr 3 (From decode) opndb_addr du_opndb_addr 3 (From decode) dstin du_dstin (From decode) 4 4 (8 ports) regfile:7 opnda_addr 3 mux a alu > rslt > dst mux b (To dcache:2 ports) eu_dcenbl ctrl eu_rdwr eu_reg_wr_vld opcode opcode_out (To regfile) load_op > opcode eu_load_op (To regfile) dcaddrin dcaddr > dcaddr 4 eu_dcaddr (To dcache) rslt 8 eu_result (To regfile) dst (To dcache) 3 eu_dst (To regfile) Figure 76 Execution unit for the pipelined RISC processor

41 Chapter Additional Design Examples 4 Page 698 clk rst_n (From eunit) eu_reg_wr_vld eu_load_op (From eunit) eu_dst 3 (From eunit) reg_wr_vld load_op dst eu_rslt (From eunit) 8 rslt regfile:7 8 regfile:7_out (8 ports: To eunit) dcdataout 8 (From dcache) dcdataout 7 Figure 77 Register file for the pipelined RISC processor

42 Chapter Additional Design Examples 42 Page 699 (From eunit) risc_dcenbl risc_rdwr (From eunit) risc_dcaddr 4 (From eunit) dcenbl rdwr dcaddr risc_rslt 8 (From eunit) dcdatain dc_dataout (To regfile) 8 dcdataout 5 Figure 78 Data cache for the pipelined RISC processor

43 Chapter Additional Design Examples 43 Page 75 Table Instructions for the Execution Unit Instruction Function nop No operation is performed add Operand A plus operand B sub Operand A minus operand B and Operand A AND operand B or Operand A OR operand B xor Operand A exclusive-or operand B inc Increment operand A by dec Decrement operand A by not Form the s complement of operand A neg Form the 2s complement of operand A shr Shift right logical operand A shl Shift left logical operand A ror Rotate right operand A rol Rotate left operand A ld Load register file from memory st Store register file to memory

44 Chapter Additional Design Examples 44 Page 76 opnda_addr regfile[] regfile7[] opnda_addr regfile[7] regfile7[7] muxa[] s s s 2 d d 7 muxa[7] s s s 2 d d 7 oprnd_a[] reg [7:] oprnd_a oprnd_a[7] opndb_addr regfile[] regfile7[] opndb_addr regfile[7] regfile7[7] muxb[] s s s 2 d d 7 muxb[7] s s s 2 d d 7 oprnd_b[] reg [7:] oprnd_b oprnd_b[7] Figure 93 Multiplexer array input to the execution unit ALU

45 Chapter Additional Design Examples 45 Page 728 +clk +dst[] +dst[] +dst[2] +reg_wr_vld +load_op +rslt[7:] +dcdataout[7:] rst_n regfile_sel DX 3: Enbl 7 reg_mux_sel MUX s d d reg_data_in[7:] regfile_enbl regfile En > Rst d d d 2 d 3 d 4 d 5 d 6 d 7 regfile7 En > Rst d d d 2 d 3 d 4 d 5 d 6 d 7 Figure 98 Register file and the associated control logic

46 Chapter Additional Design Examples 46 Page 739 clk rst_n instruction iu_pc structural risc_cpu_top risc risc risc risc iunit iunit_tb decode decode_tb eunit eunit_tb regfile regfile_tb eu_dcenbl eu_dcaddr eu_result eu_rdwr dc_dataout Figure 7 Structural organization of the RISC CPU top level Page 742 structural system_top_tb risc structural system_top clk rst_n risc icache structural risc_cpu_top risc dcache Figure 9 Structural organization

UNIVERSITY OF WISCONSIN MADISON

CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON Prof. Gurindar Sohi TAs: Minsub Shin, Lisa Ossian, Sujith Surendran Midterm Examination 2 In Class (50 minutes) Friday,