Load. Load. Load 1 0 MUX B. MB select. Bus A. A B n H select S 2:0 C S. G select 4 V C N Z. unit (ALU) G. Zero Detect.

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1 9- Write D data Load eable A address A select B address B select Load R 2 2 Load Load R R2 UX 2 3 UX Decoder D address 2 Costat i Destiatio select 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime V C N Z Load B select G select 4 Zero Detect F select R3 Bus A D select Bus D UX B UX F F Bus B UX D A data Fuctio uit Register file A B H select A B 2 S 2: C S i B Arithmetic/logic I R Shifter I L uit (ALU) G H B data Address out Data out Data i

2 9-2 Data iput A A A Data iput B A B B B -bit arithmetic/ logic uit (ALU) G G G Data output G Carry iput C i C out Carry output Operatio select S S ode select S 2 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

3 9-3 C i A X B S B iput logic Y -bit parallel adder G X Y C i S C out 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

4 T 9- TABLE 9- Fuctio Table for Arithmetic Circuit Select Iput G = ( A Y C i ) S S Y C i = C i = all s G A (trasfer) G A (icremet) B G A B (add) G A B B G A B G A B (subtract) all s G A (decremet) G A (trasfer) 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

5 9-4 Iputs Output S S B i Y i (a) Truth table S S s B i 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

6 9-5 C i S S C A B X Y FA G C A B X Y FA G C 2 A 2 B 2 X 2 Y 2 FA G 2 C 3 A 3 B 3 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime X 3 Y 3 FA C 4 G 3 C out

7 9-6 S S S S 4-to- UX S S Output Operatio A i B i G i ^^ AND OR XOR NOT 2 (b) Fuctio table 3 (a) Logic diagram 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

8 9-7 C C i C i C i C i A i B i S S A i B i S S Oe stage of arithmetic circuit 2-to- UX G A i S C i B i S Oe stage of logic circuit S S 2 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

9 T 9-2 TABLE 9-2 Fuctio Table for ALU Operatio Select S 2 S S C i Operatio Fuctio G A Trasfer A G A Icremet A G A B Additio G A B Add with carry iput of G A B A plus s complemet of B G A B Subtractio G A Decremet A G A Trasfer A X G A B AND X G A B OR X G A B XOR X G A NOT (s complemet) 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

10 9-8 B 3 B 2 B B Serial output L I R Serial output R I L S 2 U X S 2 U X S 2 U X S 2 U X S 2 H 3 H 2 H H 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

11 T 9-3 TABLE 9-3 Fuctio Table for 4-Bit Barrel Shifter Select Output S S Y 3 Y 2 Y Y Operatio D 3 D 2 D D No rotatio D 2 D D D 3 Rotate oe positio D D D 3 D 2 Rotate two positios D D 3 D 2 D Rotate three positios 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

12 9-9 D 3 D 2 D D S S 3 2 S S 3 S S U X 2 3 S S U X 2 3 S S 2 U X U X Y 3 Y 2 Y Y 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

13 9- m Write D address D data 2 m Register file m A address B address m A data B data Costat i B select UX B Bus A Bus B Address out Data out FS 4 A B V C N Fuctio uit Z F Data i 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime D select UX D

14 T 9-4 TABLE 9-4 G Select, H Select, ad F Select Codes Defied i Terms of FS Codes FS(3:) F Select G Select(3:) H Select(3:) icrooperatio XX XX XX XX XX XX XX XX X XX X XX X XX X XX XXXX XXXX XXXX F A F A F A B F A B F A B F A B F A F A F A B F A B F A B F A F B F sr B F sl B 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

15 9- RW Write D data 5 DA 4 3 D address 2 AA A address A data B address B data BA Costat i B 6 Bus A UX B Bus B Address out Data out A B V C N Z Fuctio uit 5 4 FS 3 2 Data i D UX D Bus D (a) Block diagram Pearso Educatio, Ic.. orris ao & Charles R. Kime DA AA BA B (b) Cotrol word FS D R W

16 T 9-5 TABLE 9-5 Ecodig of Cotrol Word for the Datapath DA, AA, BA B FS D RW Fuctio Code Fuctio Code Fuctio Code Fuctio Code Fuctio Code R Register F A Fuctio No Write R Costat F A Data i Write R2 F A B R3 F A B R4 F A B R5 F A B R6 F A R7 F A F A B F A B F A B F A F B F sr B F sl B 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

17 T 9-6 TABLE 9-6 Examples of icrooperatios for the Datapath, Usig Symbolic Notatio icrooperatio DA AA BA B FS D RW R R2 R3 R R2 R3 Register F A B Fuctio Write R4 sl R6 R4 R6 Register F sl B Fuctio Write R7 R7 R7 R7 F A Fuctio Write R R 2 R R Costat F A B Fuctio Write Data out R3 R3 Register No Write R4 Data i R4 Data i Write R5 R5 R R Register F A B Fuctio Write 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

18 T 9-7 TABLE 9-7 Examples of icrooperatios from Table 9-6, Usig Biary Cotrol Words icrooperatio DA AA BA B FS D RW R R2 R3 R4 sl R6 R7 R7 R R 2 Data out R3 R4 Data i R5 XXX XXX X XXX XXX XXX XXXX X XXX XXX X XXXX 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

19 9-2 Clock DA AA BA FS Pearso Educatio, Ic.. orris ao & Charles R. Kime Status_bits Costat_i X 2 B Address_out Data_out Data_i D RW reg reg reg2 reg3 reg4 reg5 reg6 reg X X

20 9-3 Program couter (PC) Istructio memory Register file 8 6 Data memory Pearso Educatio, Ic.. orris ao & Charles R. Kime

21 Opcode Destiatio register (DR) Source register A (SA) Source register B (SB) (a) Register Opcode Destiatio register (DR) Source register A (SA) Operad (OP) (b) Immediate Opcode Address (AD) (Left) Source register A (SA) Address (AD) (Right) (c) Jump ad Brach 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

22 T 9-8 TABLE 9-8 Istructio Specificatios for the Simple Computer Istructio Opcode emoic Format Descriptio Status Bits ove A OVA RD, RA R[DR] R[SA]* N, Z Icremet INC RD, RA R[DR] R[SA] + * N, Z Add ADD RD, RA, RB R[DR] R[SA] + R[SB]* N, Z Subtract SUB RD, RA, RB R[DR] R[SA] R[SB]* N, Z Decremet DEC RD, RA R[DR] R[SA] * N, Z AND AND RD, RA, RB R[DR] R[SA] R[SB]* N, Z OR OR RD, RA, RB R[DR] R[SA] R[SB]* N, Z Exclusive OR XOR RD, RA, RB R[DR] R[SA] R[SB]* N, Z NOT NOT RD, RA R[DR] R[ SA] * N, Z ove B OVB RD, RB R[DR] R[SB]* Shift Right SHR RD, RB R[DR] sr R[SB]* Shift Left SHL RD, RB R[DR] sl R[SB]* Load Immediate LDI RD, OP R[DR] zf OP* Add Immediate ADI RD, RA, OP R[DR] R[SA] + zf OP* N, Z Load LD RD, RA R[DR] [SA]* Store ST RA, RB [SA] R[SB]* Brach o Zero BRZ RA, AD if (R[SA] = ) PC PC + se AD, N, Z if (R[SA] ) PC PC + Brach o BRN RA, AD if (R[SA] < ) PC PC + se AD, N, Z Negative if (R[SA] ) PC PC + Jump JP RA PC R[SA] * For all of these istructios, PC PC + is also executed to prepare for the ext cycle. 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

23 T 9-9 TABLE 9-9 emory Represetatio of Istructios ad Data Decimal Address emory Cotets Decimal Opcode Other Fields Operatio 25 5 (Subtract) DR:, SA:2, SB:3 R R2 R (Store) SA:4, SB:5 [R4] R (Add Immediate) DR:2, SA:7, OP:3 R2 R (Brach o Zero) AD: 44, SA:6 If R6 =, PC PC 2 7 Data = 92. After executio of istructio i 35, Data = Pearso Educatio, Ic.. orris ao & Charles R. Kime

24 9-5 V C N Z Brach Cotrol PC Exted IR(8:6) IR(2:) Jump Address J L P B B C Address Istructio memory Istructio RW DA AA D Register file A B BA D A B A A A Istructio decoder B F S D R W W IR(2:) L P J B Zero fill B C CONTROL Costat i FS V C N Z Bus A A UX B Bus B Fuctio uit F B B Address out Data out Data i W Data i Address Data memory Data out 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime Bus D D UX D DATAPATH

25 9-6 Istructio Opcode DR SA SB DA AA BA B FS D RW W PL JB BC 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime Cotrol word

26 T 9- TABLE 9- Truth Table for Istructio Decoder Logic Istructio Bits Cotrol Word Bits Istructio Fuctio Type B D RW W PL JB BC Fuctio-uit operatios usig registers X X X emory read X X X emory write X X X X Fuctio-uit operatios usig register ad costat X X X Coditioal brach o zero (Z) X X Coditioal brach o egative (N) X X Ucoditioal jump X X X X 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

27 T 9- TABLE 9- Six Istructios for the Sigle-Cycle Computer Operatio Code Symbolic Name Format Descriptio Fuctio B D RW W PL JB BC ADI Immediate Add immediate operad LD Register Load memory cotet ito register ST Register Store register cotet i memory SL Register Shift left NOT Register Complemet register BRZ Jump/Brach If R[SA] =, brach to PC + se AD R[ DR] R[ SA] zf I(2:) R[ DR] [ R[ SA] ] [ R[ SA] ] R[ SB] R[ DR] sl R[ SB] R[ DR] R[ SA] If R[SA] =, PC PC se AD If R[SA], PC PC 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

28 9-7 PC.2 s Istructio memory 4 s Register file (Read).6 s UX B.2 s Fuctio uit or Data memory 4 s UX D.2 s 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime Register file.6 s (Write)

29 9-8 PS 2 PC Exted 28 Pearso Educatio, Ic CONTROL. orris ao & Charles R. Kime 4 IL 4 Cotrol State 4 6 IR Opcode DR SA SB Cotrol Logic N S P S I L D X A X B X B F S D W R W Sequece Datapath cotrol cotrol 4 DR SA SB Zero fill FS 4 DATAPATH RW 3 Register 4 address 3 logic AX BX DX 4 V C N Z Bus A D Bus D DA 6 6 Register file AA A B BA A UX B Fuctio uit F D B Bus B UX Data W Address out out B Data i Address UX D emory Data out Data i

30 NS PS I L DX AX BX FS B D R W W 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

31 T 9-2 TABLE 9-2 Cotrol-Word Iformatio for Datapath DX AX BX Code B Code FS Code D RW W Code R[DR] R[SA] R[SB] XXX Register F A FUt No Write Address out No Write R8 R8 R8 Costat F A Data i Write PC Write R9 R9 R9 F A B R R R Uused R R R Uused R2 R2 R2 F A B R3 R3 R3 F A R4 R4 R4 Uused R5 R5 R5 F A B F A B F F F F F A A B sr B sl B B Uused 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

32 T 9-3 TABLE 9-3 Cotrol Iformatio for Sequece Cotrol NS PS IL Next State Actio Code Actio Code Gives ext state of cotrol state register Hold PC No load Ic PC Load IR Brach Jump 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

33 9-2 PC PC + Σ trasitio coditios o merged arcs INF IR [PC] R[DR] R[DR] R[DR] R[SA] R[DR] R[SA] + R[SA] + R[SB] R[SA] + R[SB] + R[DR] R[SA] R[DR] R[SA] R[SB] R[DR] R[SA] R[SB] R[DR] R[DR] R[SA] R[SB] R[SA] Opcode = Opcode = R[DR] R[DR] EX [R[SA]] R[DR] R[SB] [R[SA]] zf OP R[SB] R[DR] R[SA] + zf OP Z Z PC PC se AD N PC PC se AD N PC R[SA] 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

34 T 9-4 TABLE 9-4 State Table for Two-Cycle Istructios State Opcode Iputs VCNZ Next State I L Outputs P S DX AX BX B FS D R W W Commets INF XXXXXXX XXXX EX XXXX XXXX XXXX X XXXX X IR [PC] EX XXXX INF XXX XXX XXXX X X OVA R[DR] R[SA]* EX XXXX INF XXX XXX XXXX X X INC R[DR] R[SA] + * EX XXXX INF XXX XXX XXX X ADD R[DR] R[SA] + R[SB]* EX XXXX INF XXX XXX XXX X SUB R[DR} R[SA] + R[ SB] + * EX XXXX INF XXX XXX XXXX X X DEC R[DR] R[SA] + ( )* EX XXXX INF XXX XXX XXX X AND R[DR] R[SA] R[SB]* EX XXXX INF XXX XXX XXX X OR R[DR] R[SA] R[SB]* EX XXXX INF XXX XXX XXX X XOR R[DR] R[SA] R[SB]* EX XXXX INF XXX XXX XXXX X X NOT R[DR] R[ SA] * EX XXXX INF XXX XXXX XXX X OVB R[DR] R[SB]* EX XXXX INF XXX XXX XXXX X XXXX LD R[DR] [R[SA]]* EX XXXX INF XXXX XXX XXX XXXX X ST [R[SA]] R[SB]* EX XXXX INF XXX XXXX XXXX LDI R[DR] zf OP* EX XXXX INF XXX XXX XXXX ADI R[DR] R[SA] + zf OP* EX XXX INF XXXX XXX XXXX X X BRZ PC PC + se AD EX XXX INF XXXX XXX XXXX X X BRZ PC PC + EX XXX INF XXXX XXX XXXX X X BRN PC PC + se AD EX XXX INF XXXX XXX XXXX X X BRN PC PC + EX XXXX INF XXXX XXX XXXX X X JP PC R[SA] * For this state ad iput combiatio, PC PC + also occurs. 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

35 9-2 From INF EX Opcode = R8 [R[SA]] EX Opcode = R[DR] [R8], PC PC To INF 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

36 9-22 From INF EX Z ((Opcode = ) + (Opcode = )) EX2 Z ((Opcode = ) + (Opcode = )) PC PC Opcode = R8 R8 sr R8 sl R8 R8 Z ((Opcode = ) + (Opcode = )) Opcode = Z ((Opcode = ) + (Opcode = )) R9 R9 R[SA] EX R9 EX3 zf OP PC PC Z ((Opcode = ) + (Opcode = )) Z ((Opcode = ) + (Opcode = )) EX4 (Opcode = ) + (Opcode = ) R[DR] R8, PC PC 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime To INF

37 T 9-5 TABLE 9-5 State Table for Illustratio of Istructios Havig Three or ore Cycles State Opcode Iputs VCNZ Next state Outputs I L PS DX AX BX B FS D RW W Commets EX XXXX EX XXX XXXX X X LRI R8 [R[SA]], EX EX XXXX INF XXX XXXX X X LRI R[DR] [R8], INF* EX XXX EX XXX XXXX X X SR R8 R[SA], Z: EX EX XXX INF XXX XXXX X X SR R8 R[SA], Z: INF* EX XXX EX2 XXXX XXXX X SR R9 zf OP, Z: EX2 EX XXX INF XXXX XXXX X SR R9 zf OP, Z: INF* EX2 XXXX EX3 XXXX X SR R8 sr R8, EX3 EX3 XXX EX2 XXXX X X SR R9 R9, Z: EX2 EX3 XXX EX4 XXXX X X SR R9 R9, Z: EX4 EX4 XXXX INF XXX XXXX X X SR R[DR] R8, INF* EX XXX EX XXX XXXX X X SL R8 R[SA], Z: EX EX XXX INF XXX XXXX X X SL R8 R[SA], Z: INF* EX XXX EX2 XXXX XXXX X SL R9 zf OP, Z: EX2 EX XXX INF XXXX XXXX X SL R9 zf OP, Z: INF* EX2 XXXX EX3 XXXX X SL R8 sl R8, EX3 EX3 XXX EX2 XXXX X X SL R9 R9, Z: EX2 EX3 XXX EX4 XXXX X X SL R9 R9, Z: EX4 EX4 XXXX INF XXX XXXX X X SL R[DR] R8, IF* *For this state ad iput combiatio, PC PC + also occurs. 28 Pearso Educatio, Ic.. orris ao & Charles R. Kime

Fig. 7-6 Single Bus versus Dedicated Multiplexers

Fig. 7-6 Single Bus versus Dedicated Multiplexers 7- Select SSS2 LLL2 LLL2 S 2 to MUX R R Select S 2 to MUX R S S 3 to MUX 2 us R S 2 to MUX R2 R2 (a) Dedicated multiplexers (b) Sigle us Fig. 7-6 Sigle us versus Dedicated Multiplexers 2 Pretice Hall,