Chapter 9 Computer Design Basics

Transcription

1 Logic ad Computer Desig Fudametals Chapter 9 Computer Desig asics Part Datapaths Charles Kime & Thomas Kamiski 008 Pearso Educatio, Ic. (Hyperliks are active i View Show mode) Overview Part Datapaths Itroductio Datapath Example Arithmetic Logic Uit (ALU) Shifter Datapath Represetatio ad Cotrol Word Part A Simple Computer Part Multiple Cycle Hardwired Cotrol Chapter 9 Part

2 Itroductio Computer Specificatio Istructio Set Architecture (ISA) - the specificatio of a computer's appearace to a programmer at its lowest level Computer Architecture - a high-level descriptio of the hardware implemetig the computer derived from the ISA The architecture usually icludes additioal specificatios such as speed, cost, ad reliability. Chapter 9 Part Itroductio (cotiued) Simple computer architecture decomposed ito: Datapath for performig operatios Cotrol uit for cotrollig datapath operatios A datapath is specified by: A set of registers The microoperatios performed o the data stored i the registers A cotrol iterface Chapter 9 Part 4

3 Datapaths Guidig priciples for basic datapaths: The set of registers Collectio of idividual registers A set of registers with commo access resources called a register file A combiatio of the above Microoperatio implemetatio Oe or more shared resources for implemetig microoperatios uses - shared trasfer paths Arithmetic-Logic Uit (ALU) - shared resource for implemetig arithmetic ad logic microoperatios Shifter - shared resource for implemetig shift microoperatios Chapter 9 Part 5 Datapath Example Four parallel-load registers Two mux-based register selectors Register destiatio decoder Mux for exteral costat iput uses A ad with exteral address ad data outputs ALU ad Shifter with Mux F for output select Mux D for exteral data iput Logic for geeratig status bits V, C, N, Z eable Write D data 0 Decoder D address Costat i Destiatio select M select V C N Z R0 R R R us A MD select us D 0 MUX 0 MUX D A select A address us 0 MUX A data A G select H select 4 A S :0 C S i Arithmetic/logic 0 I R Shifter I L 0 uit (ALU) G H Zero Detect 0 MF select MUX F Fuctio uit F select address 0 MUX Register file data Address out Data out Data i Chapter 9 Part 6

4 Datapath Example: Performig a Microoperatio Microoperatio: R0 R + R Apply 0 to A select to place cotets of R oto us A Apply 0 to select to place cotets of R oto data ad apply 0 to M select to place data o us Apply 000 to G select to perform additio G = us A + us Apply 0 to MF select ad 0 to MD select to place the value of G oto US D Apply 00 to Destiatio select to eable the iput to R0 Apply to Eable to force the iput to R0 to so that R0 is loaded o the clock pulse (ot show) The overall microoperatio requires clock cycle eable Write D data 0 Decoder D address Costat i Destiatio select M select V C N Z R0 R R R us A MD select us D 0 MUX 0 MUX D A select A address us 0 MUX A data A G select H select 4 A S :0 C S i Arithmetic/logic 0 I R Shifter I L 0 uit (ALU) G H Zero Detect 0 MF select MUX F Fuctio uit F select address MUX Register file data Address out Data out Chapter 9 Part 7 0 Data i Datapath Example: Key Cotrol Actios for Microoperatio Alteratives Perform a shift microoperatio apply to MF select Use a costat i a microoperatio usig us apply to M select Provide a address ad data for a memory or output write microoperatio apply 0 to eable to prevet register loadig Provide a address ad obtai data for a memory or output read microoperatio apply to MD select For some of the above, other cotrol sigals become do't cares eable Write D data 0 Decoder D address Costat i Destiatio select M select V C N Z R0 R R R us A MD select us D 0 MUX 0 MUX D A select A address us 0 MUX A data A G select H select 4 A S :0 C S i Arithmetic/logic 0 I R Shifter I L 0 uit (ALU) G H Zero Detect 0 MF select MUX F Fuctio uit F select address MUX Register file data Address out Data out Chapter 9 Part 8 0 Data i 4

5 Arithmetic Logic Uit (ALU) I this ad the ext sectio, we deal with detailed desig of typical ALUs ad shifters Decompose the ALU ito: A arithmetic circuit A logic circuit A selector to pick betwee the two circuits Arithmetic circuit desig Decompose the arithmetic circuit ito: A -bit parallel adder A block of logic that selects four choices for the iput to the adder See ext slide for diagram Chapter 9 Part 9 Arithmetic Circuit Desig (cotiued) There are oly four fuctios of to select as Y i G = A + Y: C i = 0 C i = 0 G = A G = A + G = A + G = A G = A + G = A + + G = A + + G = A What fuctios are implemeted with carry-i to the adder = 0? =? C i A X S 0 iput logic Y -bit parallel adder G X Y C i S C out Chapter 9 Part 0 5

6 Arithmetic Circuit Desig (cotiued) Addig selectio codes to the fuctios of : TALE 9- Fuctio Table for Arithmetic Circuit Select S S 0 Y Iput + + G = ( AYC i ) C i = 0 C i = all 0s G A (trasfer) G A (icremet) 0 G A (add) G A+ + 0 G A G A (subtract) all s G A (decremet) G A (trasfer) The useful arithmetic fuctios are labeled i the table Note that all four fuctios of produce at least oe useful fuctio + Chapter 9 Part Logic Circuit The text gives a circuit implemeted usig a multiplexer plus gates implemetig: AND, OR, XOR ad NOT Here we custom desig a circuit for bit G i by begiig with a truth table orgaized as a K-map ad assigig (S, S0) codes to AND, OR, etc. G i = S 0 A i i + S A i i S S 0 AND OR XOR NOT + S 0 A i i + S S 0 A i A i i Gate iput cout for MUX solutio > Gate iput cout for 0 0 above circuit < Custom desig better Chapter 9 Part 6

7 Arithmetic Logic Uit (ALU) The custom circuit has iterchaged the (S,S 0 ) codes for XOR ad NOT compared to the MUX circuit. To preserve compatibility with the text, we use the MUX solutio. Next, use the arithmetic circuit, the logic circuit, ad a -way multiplexer to form the ALU. See the ext slide for the bit slice diagram. The iput coectios to the arithmetic circuit ad logic circuit have bee bee assiged to prepare for seamless additio of the shifter, keepig the selectio codes for the combied ALU ad the shifter at 4 bits: Carry-i C i ad Carry-out C i+ go betwee bits A i ad i are coected to both uits A ew sigal S performs the arithmetic/logic selectio The select sigal eterig the LS of the arithmetic circuit, C i, is coected to the least sigificat selectio iput for the logic circuit, S 0. Chapter 9 Part Arithmetic Logic Uit (ALU) (cotiued) C 0 C i C i C i C i A i i S 0 S A i i S 0 S Oe stage of arithmetic circuit -to- 0 MUX G i A i S C i i S 0 Oe stage of logic circuit S S The ext most sigificat select sigals, S0 for the arithmetic circuit ad S for the logic circuit, are wired together, completig the two select sigals for the logic circuit. The remaiig S completes the three select sigals for the arithmetic circuit. Chapter 9 Part 4 7

8 Combiatioal Shifter Parameters Directio: Left, Right Number of positios with examples: Sigle bit: positio 0 ad positios Multiple bit: to positios 0 to positios Fillig of vacat positios May optios depedig o istructio set Here, will provide iput lies or zero fill Chapter 9 Part 5 4-it asic Left/Right Shifter Serial output L 0 I R Serial output R I L S 0 M U X S 0 M U X S 0 M U X S 0 M U X S H H Serial Iputs: Shift Fuctios: I R for right shift (S, S 0 ) = 00 Pass uchaged I L for left shift 0 Right shift Serial Outputs 0 Left shift R for right shift (Same as MS iput) Uused L for left shift (Same as LS iput) H H 0 Chapter 9 Part 6 8

9 arrel Shifter D D D D0 S0 S 0 S S0 0 S S0 0 S S0 0 S S0 M UX M UX M UX M UX Y Y A rotate is a shift i which the bits shifted out are iserted ito the positios vacated The circuit rotates its cotets left from 0 to positios depedig o S: S = 00 positio uchaged S = 0 rotate left by positios S = 0 rotate left by positios S = rotate left by positios See Table 0- i text for details Y Y0 Chapter 9 Part 7 arrel Shifter (cotiued) Large barrel shifters ca be costructed by usig: Layers of multiplexers - Example 64-bit: Layer shifts by 0, 6,, 48 Layer shifts by 0, 4, 8, Layer shifts by 0,,, See example i sectio - of the text - dimesioal array circuits desiged at the electroic level Chapter 9 Part 8 9

10 Datapath Represetatio Have looked at detailed desig of ALU ad shifter i the datapath i slide 8 Here we move up oe level i the hierarchy from that datapath The registers, ad the multiplexer, decoder, ad eable hardware for accessig them become a register file The ALU, shifter, Mux F ad status hardware become a fuctio uit The remaiig muxes ad buses which hadle data trasfers are at the ew level of the hierarchy D data m Write D address m x Register file m A address address m A data data Costat i M select 0 MUX us A us FS V C N Z 4 MD select A Fuctio uit F 0 MUX D Address out Data out Data i Chapter 9 Part 9 Datapath Represetatio (cotiued) I the register file: Multiplexer select iputs become A address ad address Decoder iput becomes D address Multiplexer outputs become A data ad data Iput data to the registers becomes D data eable becomes write The register file ow appears like a memory based o clocked flipflops (the clock is ot show) The fuctio uit labelig is quite straightforward except for FS D data Write m D address m x Register file m A address address m A data data Costat i M select 0 MUX us A us FS V C N Z 4 MD select A Fuctio uit F 0 MUX D Address out Data out Data i Chapter 9 Part 0 0

11 Defiitio of Fuctio Uit Select (FS) Codes G Select, H Select, ad MF i T of FS Codes FS(:0) MF Select G H Select(:0) Select(:0) Microoperatio XX XX XX XX XX XX XX XX X00 XX 00 0 X0 XX 00 0 X0 XX 0 0 X XX 00 XXXX 00 0 XXXX 0 0 XXXX 0 F A F A + F A + F A + + F A + F A + + F A F A F A F A F A F A F F sr F sl oolea Equatios: MFS = F F GS i = F i HS i = F i Chapter 9 Part The Cotrol Word The datapath has may cotrol iputs The sigals drivig these iputs ca be defied ad orgaized ito a cotrol word To execute a microistructio, we apply cotrol word values for a clock cycle. For most microoperatios, the positive edge of the clock cycle is eeded to perform the register load The datapath cotrol word format ad the field defiitios are show o the ext slide Chapter 9 Part

12 The Cotrol Word Fields DA AA A M FS M D R W Cotrol word Fields DA D Address AA A Address A Address M Mux FS Fuctio Select MD Mux D RW Register Write The coectios to datapath are show i the ext slide Chapter 9 Part Cotrol Word lock Diagram RW 0 Write D data 5 DA 4 AA 0 D address 8 x Register file A address A data address data 9 8 A 7 Costat i M 6 us A 0 MUX us Address out Data out A V C N Z Fuctio uit 4 FS 5 Data i MD 0 MUX D us D Chapter 9 Part 4

13 Cotrol Word Ecodig Ecodig of CotrolW DA, AA, A M FS MD RW Fuctio Code Fuctio Code Fuctio Code Fuctio Code Fuctio Code R0 000 Register 0 F A 0000 Fuctio 0 No write 0 R 00 Costat F A Data I Write R 00 F A R 0 F A R4 00 F A R5 0 F A R6 0 F A 00 R7 F A 0 F A 000 F A 00 F A 00 F A 0 F 00 F sr 0 F sl 0 Chapter 9 Part 5 Microoperatios for the Datapath - Symbolic Represetatio Microoperatio DA AA A M FS MD RW R R R R R R Register F = A + + Fuctio Write R4 sl R6 R4 R6 Register F = sl Fuctio Write R7 R7 + R7 R7 Register F = A + Fuctio Write R R0 + R R0 Costat F = A + Fuctio Write Data out R R Register No Write R4 Data i R4 Data i Write R5 0 R5 R0 R0 Register F = A Fuctio Write Chapter 9 Part 6

14 Microoperatios for the Datapath - iary Represetatio m Microoperatios from Ta iary Co o Microoperatio DA AA A M FS MD RW R R R R4 sl R6 R7 R7 + R R0 + Data out R R4 Data i R XXX XXX XXX XXX XXX 0 0 XXXX X 0 00 XXX XXX X XXXX Results of simulatio of the above o the ext slide Chapter 9 Part 7 Datapath Simulatio Clock DA AA A FS Costat_i X X M Address_out Data_out Data_i 8 8 MD RW reg0 0 reg 55 reg reg reg4 4 8 reg5 5 0 reg6 6 reg7 7 8 Status_bits 0 0 X Chapter 9 Part 8 4

15 Terms of Use All (or portios) of this material 008 by Pearso Educatio, Ic. Permissio is give to icorporate this material or adaptatios thereof ito classroom presetatios ad hadouts to istructors i courses adoptig the latest editio of Logic ad Computer Desig Fudametals as the course textbook. These materials or adaptatios thereof are ot to be sold or otherwise offered for cosideratio. This Terms of Use slide or page is to be icluded withi the origial materials or ay adaptatios thereof. Chapter 9 Part 9 5