Design. Dr. A. Sahu. Indian Institute of Technology Guwahati

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1 CS222: Processor Design: Multi Cycle Design Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati

2 Mid Semester Exam Multi Cycle design Outline Clock periods in single cycle and multicycle designs Improving resource utilization Merging memory, Removing adders Add registers and multiplexers Control ldesign for Multi cycle l CPU 2

3 Mid Semester Exam Date & time: 23 Feb 2,.AM 2.NN Venue: L2 & L3 Question pattern 4 Questions: Very Easy, 2 OK, Difficult Read & understand: Data sheet will be provided Courses: ALP, ALU Design, SC/MC processor design One Page data sheet will be provided, which will contains MIPS Instruction set, DataPath Both SingleCycle/MultiCycle, Arithmetic's unit design 3

4 Problems with single cycle design Slowest instruction pulls down theclock frequency Resource utilization is poor There are some instructions which are impossible ibl to be implemented din this manner Think which are the instructions?

5 Multi cycle Data Path 5

6 . Clock period in single cycle design R class t I t R t A t R clock period lw t I t R t A t M tr sw t I t R t A t M t I t R t A beq t + t + t I t + j t + t I

7 . Clock period in multi cycle design R class t I t R t A t R clock period lw t I t R t A t M tr R sw t I t R t A t M t I t R t A beq t + t + t I t + j t + t I

8 Improving resource utilization Can we eliminate two adders? How to share (or reuse) a resource (say ALU) in different clock cycles? Store results in registers. Of course, more multiplexing may be required! Resources in this design: RF, ALU, MEM.

9 Single Cycle Datapath ins[25 ] 28 PC+4[3 28] ja[3 ] PC ad IM ins ins[25 2] 2] ins[2 6] ins[5 ] rad rad2 wad wd 6 RF rd rd2 ALU ad rd DM wd ins[5 ] sx

10 Merge IM and DM ins[25 ] 28 PC+4[3 28] ja[3 ] PC ad ins[25 2] 2] rad rd ad rd ins[2 6] rad2 ins Mem wad rd2 wd IM ins[5 ] wd RF 6 ALU ad rd DM wd ins[5 ] sx

11 Rearrange diagram ins[25 ] 28 PC+4[3 28] ja[3 ] PC ins[25 2] 2] rad rd rd ins[2 6] rad2 Mem wad rd2 wd ins[5 ] wd RF ad ins[5 ] 6 sx ALU

12 Eliminate first adder ins[25 ] 28 PC+4[3 28] ja[3 ] PC ins[25 2] 2] rad rd ad rd Mem wd 4 ins[2 6] rad2 wad rd2 ins[5 ] wd RF ins[5 ] 6 sx ALU

13 Eliminate second adder ins[25 ] 28 PC+4[3 28] ja[3 ] + PC ins[25 2] 2] rad rd ad rd Mem wd 4 ins[2 6] rad2 wad rd2 ins[5 ] wd RF ins[5 ] 6 sx ALU

14 Rearrange diagram ins[25 ] 28 PC+4[3 28] ja[3 ] PC ins[25 2] 2] rad rd ad rd Mem wd 4 ins[2 6] rad2 wad rd2 ins[5 ] wd RF ins[5 ] 6 sx ALU

15 Introduce registers ins[25 ] 28 PC+4[3 28] ja[3 ] PC IR ins[25 2] 2] rad rd ad rd Mem wd 4 DR A ins[2 6] rad2 B wad rd2 ins[5 ] wd RF ins[5 ] 6 sx ALU RES

16 Rearrange PC input multiplexer ins[25 ] 28 PC+4[3 28] ja[3 ] PC IR 2 ins[25 2] 2] A rad ins[2 6] rd rad2 B wad rd2 ins[5 ] wd RF ad rd Mem wd 4 DR ins[5 ] 6 sx ALU RES

17 Introduce ALU inp multiplexer ins[25 ] 28 ja[3 ] PC+4[3 28] PC IR 2 ins[25 2] 2] A rad ins[2 6] rd rad2 B wad rd2 ins[5 ] wd RF ad rd Mem wd 4 DR ins[5 ] 6 sx ALU RES

18 Rearrange ALU inp2 multiplexer ins[25 ] 28 ja[3 ] PC+4[3 28] PC ad rd Mem wd IR DR ins[25 2] 2] A 2 rad ins[2 6] rd ins[5 ] ins[5 ] rad2 wad wd 6 RF rd2 sx B ALU RES

19 Introduce RF inp multiplexer ins[25 ] 28 ja[3 ] PC+4[3 28] PC ad rd Mem wd IR DR 2 ins[25 2] 2] A rad ins[2 6] rd rad2 B wad rd2 ins[5 ] RF ins[5 ] wd 6 sx ALU RES

20 Introduce Mem inp multiplexer ins[25 ] 28 ja[3 ] PC+4[3 28] PC ad rd Mem wd IR DR 2 ins[25 2] 2] A rad ins[2 6] rd rad2 B wad rd2 ins[5 ] RF ins[5 ] wd 6 sx ALU RES

21 Rearrange diagram Rearrange diagram ins[25 ] ja[3 ] 28 PC+4[3 28] 2 ins[25 ] ja[3 ] 28 ins[25 2] A 2 [ ] ins[25 2] PC[3 28] A 2 PC RF rad rad2 wad wd rd rd2 ALU ins[25 2] ins[2 6] ins[5 ] Mem ad rd wd IR RES 4 B PC RF rad rad2 wad wd rd rd2 ALU [ ] ins[2 6] ins[5 ] Mem ad rd wd IR RES 4 B wd sx 6 RES ins[5 ] DR d sx 6 RES ins[5 ] DR 2 3 4

22 Final: Multi Cycle Data Path ins[25 ] s 28 ja[3 ] PC[3 28] PC ad rd Mem wd IR DR ins[25 2] ins[2 6] ins[5 ] ins[5 ] rad rad2 wad wd 6 RF rd rd2 sx A 2 B ALU Res 22

23 Multi cycle data path Single cycle approach to multi cycle approach: improve performance and resource sharing Delays in different cycles should be balanced Single ALU and single memory used Additional registers and multiplexers required

24 Multi cycle Control 24

25 Multi cycle Control Design Break instructions into cycles Put cycle sequences together Control signal groups and micro operations Control states and signal values Control state transitions

26 Multi Cycle Data Path ins[25 ] s 28 ja[3 ] PC[3 28] PC ad rd Mem wd IR DR ins[25 2] ins[2 6] ins[5 ] ins[5 ] rad rad2 wad wd 6 RF rd rd2 sx A 2 B ALU Res 26

27 Break Instruction Execution into Cycles: R class instructionsi cycle IR = Mem[PC] PC = PC + 4 cycle 2 cycle 3 cycle 4 A = RF[IR[25 2]] B = RF[IR[2 6]] Res = A op B RF[IR[5 ]] = Res op depends upon IR[5 ]

28 Break Instruction Execution into Cycles: sw instructioni cycle IR = Mem[PC] PC = PC + 4 cycle 2 A = RF[IR[25 2]] B = RF[IR[2 6]] cycle 3 Res = A + sx(ir[5 ]) cycle 4 Mem[Res] = B

29 Break Instruction Execution into Cycles: lw instructioni cycle IR = Mem[PC] PC = PC + 4 cycle 2 A = RF[IR[25 2]] cycle 3 Res = A + sx(ir[5 ]) cycle 4 cycle 5 DR = Mem[Res] RF[IR[2 6]] = DR

30 Break Instruction Execution into Cycles: beq instructioni cycle IR = Mem[PC] PC = PC + 4 A = RF[IR[25 2]] cycle 2 B = RF[IR[2 6]] Res = PC + (sx(ir[5 ])) cycle 3 if (A == B) PC = Res

31 Break Instruction Execution into Cycles: j instructioni cycle IR = Mem[PC] PC = PC + 4 cycle 2 PC = PC[3 28] (IR[25 ]) Why have we divided execution of this instruction into two cycles?

32 Recall...Delay for { j} ins[25 ] 28 ja[3 ] PC+4[3 28] 4 + PC ad IM ins tt max + t I

33 Recall...Clock period in multi cycle design R class t I t R t A t R clock period lw t I t R t A t M tr R sw t I t R t A t M t I t R t A beq t + t + t I t + j t + t I

34 Put cycle sequences together R class sw lw beq j IR = Mem[ ] PC = IR = Mem[ ] PC = IR = Mem[ ] PC = IR = Mem[ ] PC = IR = Mem[ ] PC = A = RF[..] B = RF[..] A = RF[..] B = RF[..] A = RF[..] A = RF[..] B = RF[..] Res =..+.. PC =.. Res =..op.. Res =..+.. Res =..+.. if(..==..) PC =.. RF[..] =.. Mem[ ] =.. DR = Mem[ ] RF[..] = DR these can be merged

35 After merging fetch cycle IR = Mem[ ] PC = R class sw lw beq j A = RF[..] B = RF[..] A = RF[..] B = RF[..] A = RF[..] A = RF[..] B = RF[..] Res =..+.. PC =.. Res =..op.. Res =..+.. Res =..+.. if(..==..) PC =.. RF[..] =.. Mem[ ] =.. DR = Mem[ ] Opcode is available only second cycle onwards. RF[..] = DR Split from 3 rd cycle onwards after decoding opcode.

36 With a common decoding cycle IR = Mem[ ] PC = A = RF[..] B = RF[..] Res =..+.. R class sw lw beq j Res =..op.. Res =..+.. Res =..+.. if(..==..) PC =.. PC =.. RF[..] =.. Mem[ ] =.. DR = Mem[ ] RF[..] = DR

37 lw, sw can split after third cycle IR = Mem[ ] PC = A = RF[..] B = RF[..] Res =..+.. R class sw / lw beq j Res =..op.. Res =..+.. if(..==..) sw lw PC =.. RF[..] =.. Mem[ ] =.. DR = Mem[ ] PC =.. RF[..] = DR

38 Control signals in multi cycle DP PW PC IorD MR MW RW ad Mem wd IW rd DW IR DR ins[25 2] ins[2 6] ins[5 ] Rdst ins[5 ] rad rad2 wad wd 6 M2R RF AW rd rd2 sx ins[25 ] Asrc 28 ja[3 ] PC[3 28] A Z 2 B ALU RW ReW 4 BW 3 Res Psrc op 2 3 Asrc2

39 Micro operations and control signals PC group Micro operation PWu PWc Psrc PC = PC + 4 PCinc X if (A == B) PC = Res branch PC=PC[3 28] (IR[25 ]) jump X 2 default nop X PW = PWu + Z. PWc

40 Micro operations and control signals Mem group Micro operation MW MR IorD IW DW IR = Mem[PC] fetch DR = Mem[Res] m_rd Mem[Res] = B mwr m_wr default nop X

41 Micro operations and control signals RF group Micro operation RW Rdst M2R AW BW A = RF[IR[25 2]] [ X X ra B = RF[IR[2 6]] rt2b X X RF[IR[5 ]] = Res rerd RF[IR[2 6]] = DR mem2rt default nop X X

42 Micro operations and control signals ALU group Micro operation opc Asrc Asrc2 ReW PC = PC + 4 PCinc Res = A op B arith 2 Res = A + sx(ir[5 ]) Mdd Maddr 2 Res = PC + (sx(ir[5 ])) Paddr 3 if (A == B) PC = Res branch default nop X X X

43 Control states and micro operations fetch cs PCinc c ra cs rt2b Paddr R class sw / lw beq j cs4 sw arith Maddr branch jump rerd m_wr m_rd cs3 cs5 cs6 cs7 lw mem2rt 2t cs8 cs9

44 Control states and signal values PC grp Mem grp RF grp ALU grp cs PCinc fetch nop PCinc cs nop nop ra,rt2b Paddr c nop nop nop arith cs3 nop nop rerd nop cs4 nop nop nop Maddr cs5 nop m_wr nop nop cs6 nop m_rd mrd nop nop cs7 nop nop mem2rt nop cs8 branch nop nop branch cs9 jump nop nop nop

45 Control state transitions R class sw lw beq j cs cs cs cs cs cs cs c cs4 cs4 cs8 cs9 c cs3 X X X X cs3 cs X X X X cs4 X cs5 cs6 X X cs5 X cs X X X cs6 X X cs7 X X cs7 X X cs X X cs8 X X X cs X cs9 X X X X cs

46 Summary Instructions expressed as sequences of micro operations Control signal are grouped Micro operations define values of control signals of a group Control states associated with micro operations Control state transitions depend upon opcode

47 47

Processor Design & ALU Design

Processor Design & ALU Design 3/8/2 Processor Design A. Sahu CSE, IIT Guwahati Please be updated with http://jatinga.iitg.ernet.in/~asahu/c22/ Outline Components of CPU Register, Multiplexor, Decoder, / Adder, substractor, Varity of