COMP303 Computer Architecture Lecture 11. An Overview of Pipelining

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1 COMP303 Compute Achitectue Lectue 11 An Oveview of Pipelining

2 Pipelining Pipelining povides a method fo executing multiple instuctions at the same time. Laundy Example: Ann, Bian, Cathy, Dave each have one load of clothes to wash, dy, and fold Washe takes 30 minutes A B C D Dye takes 40 minutes Folde takes 20 minutes

3 Sequential Laundy 6 PM Midnight Time T a s k O d e A B C D Sequential laundy takes 6 hous fo 4 loads If they leaned pipelining, how long would laundy take?

4 Pipelined Laundy: Stat wok ASAP 6 PM Midnight Time T a s k O d e A B C D Pipelined laundy takes 3.5 hous fo 4 loads

5 Pipelining Lessons T a s k O d e 6 PM Time A B C D Pipelining doesn t help latency of single task, it helps thoughput of entie wokload Pipeline ate limited by slowest pipeline stage Multiple tasks opeating simultaneously using diffeent esouces Potential speedup = Numbe pipe stages Unbalanced lengths of pipe stages educes speedup Time to fill pipeline and time to dain it educes speedup Stall fo Dependences

6 Total Time fo Eight Instuctions Inst. class Inst. fetch Registe ead opeation Data access Registe wite Total time Load wod 2 ns 1 ns 2 ns 2 ns 1 ns 8 ns Stoe wod 2 ns 1 ns 2 ns 2 ns 7 ns R-type 2 ns 1 ns 2 ns 1 ns 6 ns Banch 2 ns 1 ns 2 ns 5 ns R-type instuctions: add, sub, and, o, slt

7 Single Cycle vs. Pipelined Execution Pogam execution ode lw $1,10($0) lw $2,20($0) lw $3,30($0) Inst. fetch Reg Data access Reg 8 ns Inst. fetch Reg Data access Reg 8 ns Inst. fetch 8 ns Pogam execution ode Inst. lw $1,10($0) fetch lw $2,20($0) lw $3,30($0) 2 ns Reg Inst. fetch 2 ns Reg Inst. fetch Data access Reg Reg Data access Reg Data access Reg Total: 24 ns 2 ns 2 ns 2 ns 2 ns 2 ns Total: 14 ns

8 Pipelining Speedup If the stages ae pefectly balanced: Time between instuctions pipelined = Time between instuctions nonpipelined Numbe of pipeline stages Potential speedup = Numbe of pipeline stages In pevious example, 3 instuctions takes 14 ns. If we would add 1000 instuctions then each instuction will add 2 ns to the total execution time: Total execution time pipelined = = 2014 ns Total execution time nonpipelined = 1003 * 8 = 8024 ns 8024 / 2014 = 3.98 ~ 8 / 2 =

9 The Five Stages of the Load Instuction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Load Ifetch Reg/Dec Exec Mem W Ifetch: Instuction Fetch Fetch the instuction fom the Instuction Memoy Reg/Dec: Registes Fetch and Instuction Decode Exec: Calculate the memoy addess Mem: Read the data fom the Data Memoy W: Wite the data back to the egiste file

10 Pipelined Execution Time IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB Pogam Flow IFetch Dcd Exec Mem WB On a pocesso multiple instuctions ae in vaious stages at the same time. Assume each instuction takes five cycles

11 Single Cycle, Multiple Cycle, vs. Pipeline Clk Cycle 1 Cycle 2 Single Cycle Implementation: Load Stoe Waste Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Clk Multiple Cycle Implementation: Load Ifetch Reg Exec Mem W Stoe Ifetch Reg Exec Mem R-type Ifetch Pipeline Implementation: Load Ifetch Reg Exec Mem W Stoe Ifetch Reg Exec Mem W R-type Ifetch Reg Exec Mem W

12 Gaphically Repesenting Pipelines Time (clock cycles) I n s t. Inst 0 Inst 1 Can help with answeing questions like: How many cycles does it take to execute this code? What is the doing duing cycle 4? Ae two instuctions tying to use the same esouce at the same time?

13 Why Pipeline? Because the esouces ae thee! Time (clock cycles) I n s t. O d e Inst 0 Inst 1 Inst 2 Inst 3 Inst 4

14 Why Pipeline? Suppose 100 instuctions ae executed The single cycle machine has a cycle time of 45 ns The multicycle and pipeline machines have cycle times of 10 ns The multicycle machine has a CPI of 3.6 Single Cycle Machine 45 ns/cycle x 1 CPI x 100 inst = 4500 ns Multicycle Machine 10 ns/cycle x 3.6 CPI x 100 inst = 3600 ns Ideal pipelined machine 10 ns/cycle x (1 CPI x 100 inst + 4 cycle dain) = 1040 ns Ideal pipelined vs. single cycle speedup 4500 ns / 1040 ns = 4.33 What has not yet been consideed?

15 Can pipelining get us into touble? Yes: Pipeline Hazads stuctual hazads: attempt to use the same esouce (hadwae unit) two diffeent ways at the same time E.g., two instuctions ty to ead the same memoy at the same time data hazads: attempt to use item befoe it is eady instuction depends on esult of pio instuction still in the pipeline add 1, 2, 3 sub 4, 2, 1 contol hazads: attempt to make a decision befoe condition is evaluated banch instuctions beq 1, 2, loop add 3, 4, 5 Can always esolve hazads by waiting pipeline contol must detect the hazad take action (o delay action) to esolve hazads

16 Single Memoy is a Stuctual Hazad Time (clock cycles) I n s t. O d e Load Inst 1 Inst 2 Inst 3 Inst 4 Mem Reg Mem Reg Detection is easy in this case! (ight half highlight means ead, left half wite)

17 What s the Solution? Solution 1: Use sepaate instuction and data memoies Solution 2: Allow memoy to ead and wite moe than one wod pe cycle Solution 3: Stall

18 Solution 3: Stall Time (clock cycles) I n s t. O d e Load Inst 1 Inst 2 nop Inst 3 Inst 4 bubble bubble bubble bubble bubble Mem Reg Mem Reg

19 Contol Hazad Solutions Stall: wait until decision is clea It is possible to move up decision to 2nd stage by adding exta hadwae to check egistes as being ead I n s t. O d e Add Beq Load Time (clock cycles) Mem Reg Mem Reg Impact: 2 clock cycles pe banch instuction => slow

20 Contol Hazad Solutions Pedict: guess one diection then back up if wong Pedict not taken I n s t. O d e Add Beq Load Time (clock cycles) Mem Reg Mem Reg Impact: 1 clock cycle pe banch instuction if ight, 2 if wong (ight - 50% of time) Moe dynamic scheme: histoy of 1 banch (- 90%)

21 Contol Hazad Solutions Redefine banch behavio (takes place afte next instuction) delayed banch I n s t. O d e Add Beq Misc Load Time (clock cycles) Mem Impact: 1 clock cycles pe banch instuction if can find instuction to put in slot (- 50% of time) Reg Mem Reg Mem Reg Mem Reg

22 Data Hazad on 1 Poblem: 1 cannot be ead by othe instuctions befoe it is witten by the add. add 1, 2, 3 sub 4, 1, 3 and 6, 1, 7 o 8, 1, 9 xo 10, 1, 11

23 Data Hazad on 1: Dependencies backwads in time ae hazads I n s t. O d e Time (clock cycles) IF ID/RF EX MEM WB add 1,2,3 sub 4,1,3 and 6,1,7 o 8,1,9 xo 10,1,11 Im Reg Dm Reg

24 Data Hazad Solution: Fowad esult fom one stage to anothe I n s t. O d e Time (clock cycles) IF ID/RF EX MEM WB add 1,2,3 sub 4,1,3 and 6,1,7 o 8,1,9 xo 10,1,11 Im Reg Dm Reg o instuction is OK if define ead/wite popely

25 Fowading (o Bypassing): What about Loads Dependencies backwads in time ae hazads Time (clock cycles) IF ID/RF EX MEM WB lw 1,0(2) sub 4,1,3 Can t solve with fowading: Must delay/stall instuction dependent on loads

CMP N 301 Computer Architecture. Appendix C

CMP N 301 Computer Architecture Appendix C Outline Introduction Pipelining Hazards Pipelining Implementation Exception Handling Advanced Issues (Dynamic Scheduling, Out of order Issue, Superscalar, etc)