CMP 334: Seventh Class

Transcription

1 CMP 334: Seventh Class Performance HW 5 solution Averages and weighted averages (review) Amdahl's law Ripple-carry adder circuits Binary addition Half-adder circuits Full-adder circuits Subtraction, negative numbers, signed arithmetic A B = A + B For next class: HW 6; read A.3-4, 2.1-5, 3.1-2

2 HW 5: Performance Problems 1) Computer A has a 5 GHz clock and executes program P in 3 seconds with an average CPI (cycles per instruction) of 3.. How many instructions does it execute for program P? 2) Computer B has a 2 GHz clock. It executes P with the same number of instructions as computer A with an average CPI 1.. How long does it take to execute P? 3) Compare the performance of computer B and computer A on program P. Which is faster? by how much? 4) A new compiler for computer A compiles program P so that it executes only half as many instructions. Unfortunately, the CPI for computer A on these instructions is 4.. How long does it take to execute the newly compiled program? 5) Compare the performance of computer B (with the old compiler) to computer A (with the new compiler) on program P. Which is faster? by how much?

3 Performance Equations Performance inverse of execution time performance: P x 1 T x relative performance: P x P y = T y T x CPU time equation T CPU (execution ) = # instructions execution Amdahl's law # cycles instruction # seconds cycle T new = fraction affected T old improvement + fraction not affected T old

4 Processor Performance Equations T X = # instructions X CPI X cycletime X T X = # instructions X CPI X clockrate X P X P Y = T Y T X = # instructions Y CPI Y cycletime Y # instructions X CPI X cycletime X P X P Y = T Y T X = # instructions Y CPI Y clockrate X # instructions X CPI X clockrate Y

5 HW 5.1 Instruction Count Computer A has a 5 GHz clock and executes program P in 3 seconds with an average CPI (cycles per instruction) of 3.. How many instructions does it execute for program P? T A = # instructions A CPI A clockrate A 3 seconds = # instructions A 3. cycles / instruction 5 GHz # instructions A = 3 seconds 5 19 cycles / second 3. cycles / instruction # instructions A = instructions

6 HW 5.2 Execution Time Computer B has a 2 GHz clock. It executes P with the same number of instructions as computer A (5 1 9 instructions) with an average CPI 1.. How long does it take to execute P? T B T B T B T B = # instructions B CPI B clockrate B = 5 19 instructions 1. cycles / instruction 2 GHz = 5 19 instructions 1 cycles / instruction cycles / second = 25 seconds

7 HW 5.3 Relative Performance Compare the performance of computer B and computer A on program P. Which is faster? by how much? P B P A = T A T B = 3 seconds 25 seconds = 1.2 B is 1.2 times faster than A.

8 HW 5.4 Execution Time A new compiler for computer A compiles program P so that it executes only half as many instructions. Unfortunately, the CPI for computer A on these instructions is 4.. How long does it take to execute the newly compiled program? T A ' = # instructions A' CPI A ' clockrate A' 1 2 # instructions A 4. cycles / instruction T A ' = clockrate A T A ' = instructions 4. cycles / instruction cycles / second T A ' = 1 seconds = 2 seconds 5

9 HW 5.5 Relative Performance Compare the performance of computer B (with the old compiler) to computer A' (A with the new compiler) on program P. Which is faster? by how much? P A' P B = T B T A' = 25 seconds 2 seconds = 1.25 A' is 1.25 times faster than B. P A' P A = T A T A' = 3 seconds 2 seconds = 1.5 A' is 1.5 times faster than A.

10 Averages and Weighted Averages Given values: {v 1, v 2, v N } & weights: {w 1, w 2, w N } average: v N i=1 N v i total weight: N W i = 1 w i normalized weight: q i w i W N ( i = q i = 1 ) weighted average: i=1 N N i=1 w i v i w i = N i=1 w i v i W N = i=1 w i W v i N = i=1 q i v i

11 Typical Instruction Statistics Instruction types, frequencies, and execution times 5% ALU instructions 5 CPI 3% Memory instructions 2% Load 8 CPI 1% Store 6 CPI 2% Branch instructions 1 CPI.5% Special instructions

12 Average Cycles Per Instruction (Weighted) average CPI = q ALU T ALU + q Load T Load + q Store T Store + q Branch T Branch = = = 6.7 cycles approximation: 2 / Execution time fraction by instruction type ALU 2.5 / 6.7 ~ 37.5% Load 1.6 / 6.7 ~ 24.% Store.6 / 6.7 ~ 9.% Branch 2. / 6.7 ~ 3.%

13 CPU Time Equation T CPU (execution ) = # instructions execution # cycles instruction # seconds cycle If T CPU (execution ) 2 seconds, cycle time = 1 9 seconds 2 seconds # instructions seconds 2 # instructions instruction time = # seconds instruction = # cycles instruction # seconds cycle

14 Performance Equations Performance inverse of execution time performance: P x 1 T x relative performance: P x P y = T y T x CPU time equation T CPU (execution ) = # instructions execution Amdahl's law # cycles instruction # seconds cycle T new = fraction affected T old improvement + fraction not affected T old

15 Amdahl's Law old time (12) affected (8) unaffected (4) SpeedUp (1.6) improved (5) unaffected (4) new time (9) T old = affected + unaffected T new = improved + unaffected SpeedUp = affected / improved Overall SpeedUp = P new /P old = T old /T new (fraction affected) F a = affected / T old (fraction unaffected) F a = unaffected / T old

16 Improving Race Car Performance miles miles/hours cruising 9 9 other 1 5 Race time = 9/9 + 1/5 = 12 hours Change #1: 1.11 x improvement in cruising speed Change #2: 2. x improvement in other speed

17 Change # 1 T old = 12 hours fa =.9 (fraction affected = affected/total = fa =.1 (fraction unaffected = unaffected/total = su = 1.11 (speedup for affected) 9 miles ) 1 miles 1 miles 1 miles ) T new = fa T old su + fa T old T new = = 1.93 hours

18 Change # 2 T old = 12 hours fa =.1 (fraction affected = affected/total = fa =.9 (fraction unaffected = unaffected/total = su = 2. (speedup for affected) 1 miles ) 1 miles 9 miles 1 miles ) T new = fa T old su + fa T old T new = = 11.4 hours

19 Change # 1 wrong! T old = 12 hours fa =.9 (fraction affected = affected/total = fa =.1 (fraction unaffected = unaffected/total = su = 1.11 (speedup for affected) 9 miles ) 1 miles 1 miles 1 miles ) T new = fa T old su + fa T old T new = = 1.93 hours

20 Change # 2 wrong! T old = 12 hours fa =.1 (fraction affected = affected/total = fa =.9 (fraction unaffected = unaffected/total = su = 2. (speedup for affected) 1 miles ) 1 miles 9 miles 1 miles ) T new = fa T old su + fa T old T new = = 11.4 hours

21 Change # 1 correct T old = 12 hours fa =.833 (fraction 1 hours affected = affected/total = 12 hours = 5 ) 6 fa =.167 (fraction unaffected = unaffected/total = 2 hours 12 hours = 1 ) 6 su = 1.11 (speedup for affected) T new = fa T old su T new fa T old = 11 hours

22 Change # 2 correct T old = 12 hours fa =.167 (fraction affected = affected/total = 2 hours 12 hours = 1 ) 6 fa =.833 (fraction unaffected = unaffected/total = su = 2. T new (speedup for affected) = fa T old su T new fa T old 1 hours 12 hours = 5 6 ) = 11 hours

23 Average Cycles Per Instruction (Weighted) average CPI = q ALU T ALU + q Load T Load + q Store T Store + q Branch T Branch = = = 6.7 cycles approximation: 2 / Execution time fraction by instruction type ALU 2.5 / 6.7 ~ 37.5% Load 1.6 / 6.7 ~ 24.% Store.6 / 6.7 ~ 9.% Branch 2. / 6.7 ~ 3.%

24 CPU Time Equation T CPU (execution ) = # instructions execution # cycles instruction # seconds cycle If T CPU (execution ) 2 seconds, cycle time = 1 9 seconds 2 seconds # instructions seconds 2 # instructions instruction time = # seconds instruction = # cycles instruction # seconds cycle

25 Amdahl's Law 1 T new = fraction affected T old improvement + fraction not affected T old Improvement X reduces ALU instruction CPI from 5 to 4 T X = fraction affected 2 sec improvement + fraction not affected 2 sec

26 Amdahl's Law 1 (wrong!) T new = fraction affected T old improvement + fraction not affected T old Improvement X reduces ALU instruction CPI from 5 to 4 T X = fraction affected 2 sec improvement + fraction not affected 2 sec T X = sec = 8 +1 sec = 18 sec

27 ( Amdahl's Law 1 T new = fraction affected T old improvement + fraction not affected T old Improvement X reduces ALU instruction CPI from 5 to 4 T X = fraction affected 2 sec improvement + fraction not affected 2 sec T X = ) sec ( ) sec = 18.6 sec

28 ( Amdahl's Law 2 T new = fraction affected T old improvement + fraction not affected T old Improvement Y reduces Load instruction CPI from 8 to 4 T Y = fraction affected 2 sec improvement + fraction not affected 2 sec T Y = )sec ( ) sec = 17.7 sec

29 ( Amdahl's Law 3 T new = fraction affected T old improvement + fraction not affected T old Improvement Z reduces Store instruction CPI from 6 to 2 T Z = fraction affected 2 sec improvement + fraction not affected 2 sec T Z = )sec ( ) sec = 18.9 sec

30 ( Amdahl's Law 4 T new = fraction affected T old improvement + fraction not affected T old Improvement W reduces Branch instruction CPI from 1 to 5 T W = fraction affected 2 sec improvement + fraction not affected 2 sec T W = )sec ( ) sec = 17.1 sec

31 Amdahl's Law old time (12) affected (8) unaffected (4) SpeedUp (1.6) improved (5) unaffected (4) new time (9) T old = affected + unaffected T new = improved + unaffected SpeedUp = affected / improved Overall SpeedUp = P new /P old = T old /T new (fraction affected) F a = affected / T old (fraction unaffected) F a = unaffected / T old

32 Amdahl's Law Overall SpeedUp performance: P x 1 T x relative performance: P x P y = T y T x P X P old = T old T X = P Y P old = T old T Y = P Z P old = T old T Z = P W P old = T old T W =

33 Amdahl's Law Overall SpeedUp P new P old = T old T new P new P old = fa T old su T old + fa T old P new P old = 1 fa su + fa

34 Human Addition (Binary)

35 Binary Addition

36 Binary Addition

37 Binary Addition

38 Binary Addition

39 Binary Addition

40 Binary Addition

41 Binary Addition

42 Binary Addition

43 64-Bit Computer Addition a s b bit adder.. a 63 b 63 s 63 C

44 4-Bit Computer Addition a b 1-bit adder s a 1 b 1 a 2 b 2 1-bit adder 4-bit adder half 1-bit adder s 1 s 2 a 3 b 3 1-bit adder s 3 c

45 4-Bit Ripple Carry Adder a b 1-bit adder s a 1 b 1 a 2 b 2 1-bit adder 4-bit adder half 1-bit adder s 1 s 2 a 3 b 3 1-bit adder s 3 c

46 4-Bit Ripple Carry Adder a b 1-bit adder s a 1 b 1 1-bit adder s 1 a 2 b 2 half 1-bit adder s 2 a 3 b 3 1-bit adder s 3 c

47 4-Bit Ripple Carry Adder a b s a 1 b 1 full adder s 1 a 2 b 2 full adder s 2 a 3 b 3 full adder s 3 c

48 1-Bit Computer Addition (take 1) a s b c

49 Half Adder Truth Table a b c s c = ab s = ab + ab

50 Half Adder Circuit a s b c

51 1-Bit Computer Addition (take 2) c a b full adder s i c'

52 Full Adder # a b c c' s s' = abc + abc + abc + s' = abc c' = abc + abc + abc + c' = abc + abc + abc c' = abc + abc + abc + c' = abc + abc + abc c' = bc + ac + ab

53 Full Adder # a b c c' s s' = abc + abc + abc + s' = abc c' = abc + abc + abc + c' = abc + abc + abc c' = abc + abc + abc + c' = abc + abc + abc c' = bc + ac + ab

54 Full Adder # a b c c' s s' = abc + abc + abc + s' = abc c' = abc + abc + abc + c' = abc + abc + abc c' = abc + abc + abc + c' = abc + abc + abc c' = bc + ac + ab

55 Full Adder # a b c c' s s' = abc + abc + abc + s' = abc c' = abc + abc + abc + c' = abc + abc + abc c' = abc + abc + abc + c' = abc + abc + abc c' = bc + ac + ab

56 s' = abc + abc + abc + abc c' = ab + ac + bc c a b full adder r c'

57 s' = abc + abc + abc + abc c' = ab + ac + bc c a b r c' full adder

58 Full Adder?? c a b s full adder c'

59 Full Adder?? c a s b x z y full adder c'

60 Full Adder Implementation?? # a b c x y z c' s c a b full adder x y u v c s z c' c = uv s = uv + uv s

61 Full Adder Implementation! # a b c x y z c' s c a b full adder x y u v c s z c' c = uv s = uv + uv s

62 A Full Adder c a b s i Full Adder c'

63 A Full Adder c a b s i Full Adder c'

64 Initial adder half or full? a b half? s a 1 b 1 full adder s 1 a 2 b 2 full adder s 2 a 3 b 3 full adder s 3 c

65 Full Initial adder? Con Pro Superfluous wires and gates General simplicity Avoid special cases where ever practical Simplifies addition of big integers Big Integer: N = x k J k x 2 J 2 + x 1 J 1 + x J Where J 2 32 Like base 1 but with sixteen billion billion fingers Simplifies subtraction

66 4-Bit Ripple Carry Adder c -1 a b half full adder s a 1 b 1 half full adder adder s 1 a 2 b 2 half full adder s 2 a 3 b 3 full adder s 3 c 3

67 4-Bit Ripple Carry Adder c -1 a b half full adder 4-bit adder s a 1 b 1 half full adder adder s 1 a 2 b 2 half full adder s 2 a 3 b 3 full adder s 3 c 3

68 4-Bit Ripple Carry Adder c -1 a b half full adder s a 1 b 1 a 2 b 2 half full adder adder 4-bit adder half full adder s 1 s 2 a 3 b 3 full adder s 3 c 3

69 8-Bit Ripple Carry Adder c -1 a b a 1 b 1 a 2 b 2 a 3 b 3 a 4 b 4 a 5 b 5 a 6 b 6 a 7 b 7 half full adder full adder 4-bit adder 8-bit adder half full adder half full c 3 half full adder full adder 4-bit adder half full adder half full s s 1 s 2 s 3 s 4 s 5 s 6 s 7 c 7

70 64-Bit Ripple Carry Adder c -1 a s b bit adder.. a 63 b 63 s 63 c 63

71 Fixed Width Binary Addition

72 Fixed Width Binary Addition

73 Fixed Width Binary Addition

74 Fixed Width Binary Addition

75 Fixed Width Binary Addition

76 Fixed Width Binary Addition Carry out

77 Fixed Width Binary Addition Carry out Carry in

78 Non-Negative Numbers Subtraction A B A ~ B A B (ordinary arithmetic) A < B 1) B ~ B = 2) (A ~ B) + C = (A + C) ~ B ~B ~ B = 2 n B = B + 1 ~B pseudoinverse of B A ~ B A + B + 1

79 Fixed Width Binary Addition Borrow Carry in

80 Negative Number Representation Alternatives 1. Sign-magnitude 2. Bias How would it help Complicates arithmetic 3. 1's complement Too many zeros 4. 2's complement

81 Negative Number Representation Unsigned numbers:.. 2 N - 1 Signed number alternatives 1. Sign-magnitude: 2 N N-1 1 How would this help? 2. Bias: bias.. 2 N 1 bias Complicates arithmetic (a-bias + b-bias) = (a + b)-bias)-bias 3. 1's complement: 2 N N and 's complement: 2 N N-1 1

82 Negative Number Representation # binary sign magnitude bias (8) 1's complement 2's complement A B C D E F

83 1's Complement Arithmetic The 9's complement, d, of a decimal digit d is 9 d The 9's complement, X, of a 4-digit X is 9999 X The 1's complement, X, of X is X + 1 X = X + 1 = 9999 X +1 = 1 X convention: X is positive and Y is negative iff X < 5 Y < 1 Y Y and X Y = X + Y unless Overflow sign(x) = sign(y) sign(x + Y) Overflow sign(x) sign(y) = sign(x Y)

84 1 = 's Complement Example 1 = = = 12 2 = = = = = = = = 98 = overflow = 6 = =

85 2's Complement Arithmetic The 1's complement, b, of a binary bit b is 1 d The 1's complement, X, of a 4-bit X is 1111 X The 2's complement, X, of X is X + 1 X = X + 1 = 1111 X +1 = 1 X convention: X is positive and Y is negative iff X < 2 N-1 Y < 2 N Y Y and X Y = X + Y unless Overflow sign(x) = sign(y) sign(x + Y) Overflow sign(x) sign(y) = sign(x Y)

86 Unsigned Integers = 2 N = 2 N = 2 N = 2 N = 4 = = 3 = = 2 = = 1 = 2 = = = = 1 = = 2 = 2 1 = = 3 = = 4 = = 5 = = 2 N = 2 N = 2 N = 2 N N Bit Integers (N = 8) Signed Integers

87 Negative Number Representation # binary sign magnitude bias (-7) 1's complement 2's complement A B C D E F

88 Basic Processor Model registers SYSTEM BUS A MUX A bus C MUX B MUX B bus ALU C Bus PC IR

89 Basic Processor Model registers SYSTEM BUS Combinational Core A MUX A bus C MUX B MUX B bus ALU C Bus PC IR

90 Building Blocks Arithmetic / Logical Unit AND, OR, and NOT gates Inverters, Decoders, Multiplexers Inputs (operands): A and B buses Output (result): C bus Logical Bitwise: A, A & B, A B, A ^ B, A B, A B,... Arithmetic A + B, A B, A ٠ B, A div B, A mod B Comparison A < B, A = B, A B, etc. and X <, X =, X, etc.

91 TINY Arithmetic / Logical Unit Building Blocks AND, OR, and NOT gates Inverters, Decoders, Multiplexers Inputs (operands): A and B buses Output (result): C bus Logical Bitwise: A, A & B, A B, A ^ B, A B, A B,... Arithmetic A + B, A B, A ٠ B, A div B, A mod B Comparison A < B, A = B, A B, etc. and X <, X =, X, etc.

92 Muxes, Buses, and ALU ALU inputs (operands): A and B buses ALU output (result): C bus Logical Bitwise: A, A & B, A B, A ^ B, A B, A B,... Arithmetic A + B, A B, A ٠ B, A div B, A mod B Comparison A < B, A = B, A B, etc. and X <, X =, X, etc. Combinational building blocks AND, OR, and NOT gates Inverters, Decoders, Multiplexers

93 Inverters, Decoders, Multiplexer Inverter: select data input or its negation 1 data input 1 selector input 1 output Decoder: select unique output to be 1 (true) N selector inputs 2 N outputs Multiplexer: select unique data input to be output 2 N data inputs N selector inputs 1 output

94 The TINY Computer A bus B bus ALU C Bus B MUX A MUX C MUX SYSTEM BUS MAR x x x x x x x x x x x x x x x xffff MDR Z N C O registers $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F PC IR

95 The TINY Computer A bus B bus ALU C Bus B MUX A MUX C MUX SYSTEM BUS MAR x x x x x x x x x x x x x x x xffff MDR Z N C O registers $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F PC IR

96