EC 413 Computer Organization
|
|
- Gillian Ward
- 5 years ago
- Views:
Transcription
1 EC 413 Computer Organization rithmetic Logic Unit (LU) and Register File Prof. Michel. Kinsy
2 Computing: Computer Organization The DN of Modern Computing Computer CPU Memory System LU Register File Disks Main Memory Cache Comparator dder Multiplier Latch Decoder Controller RM Decoder Cacheline Line Selection Logic it Cell
3 rithmetic Logic Unit (LU) Recall our binary adder Cin Sum Cin Sum Cin Cout Single it Full dder (F) Cout
4 rithmetic Logic Unit (LU) How to support the 32 bits operations in the MIPS IS? Cin Sum Cout Single it Full dder (F)
5 rithmetic Logic Unit (LU) How to support the 32 bits operations in the MIPS IS? c 3 c 2 c 1. C in Cin Sum Cout Single it Full dder (F) C out S 3 S 2 S 1 S
6 rithmetic Logic Unit (LU) How to support the 32 bits operations in the MIPS IS? c 3 c 2 c 1. C in Cin Sum C out S 3 S 2 S 1 S Single it Full dder (F) Cout F F F F C 4 C S 3 C 3 S 2 C 2 S 1 1 S
7 rithmetic Logic Unit (LU) C out LU (dder) C in c 3 c 2 c 1 C in C out S 3 S 2 S 1 S S 3 S 2 S 1 S F F F F C 4 C S 3 C 3 S 2 C 2 S 1 1 S
8 rithmetic Logic Unit (LU) Carry Propagate inary dder x 7 x 6 x 5 x 4 y7 y 6 y 5 y 4 x 3 x 2 x 1 x y3 y 2 y 1 y C y C C y C S 3 S 2 S 1 S S 3 S 2 S 1 S S 7 S 6 S 5 S 4 S 3 S 2 S 1 S
9 rithmetic Logic Unit (LU) There are many ways to build these components dders Time Complexity Space Complexity Type Time Space Ripple Carry O(n) O(n) Carry Lookahead Carry Skip Carry Select O(log n) O(n log n) ( n ) ( n ) O(n) O(n)
10 Overflow Unsigned inary Numbers x 3 x 2 x 1 x y 3 y 2 y 1 y F F F F Carry 2 s Complement Numbers C 4 C S 3 C 3 S 2 C 2 S 1 1 S x 3 x 2 x 1 x y 3 y 2 y 1 y F F F F Overflow C 4 C S 3 C 3 S 2 C 2 S 1 1 S
11 rithmetic Logic Unit (LU) Preform 2 s complement subtraction with binary adder x y = x + (-y) = x + y + 1 x 3 x 2 x 1 x y 3 y 2 y 1 y C y inary dder S 3 S 2 S 1 S C 1 S 3 S 2 S 1 S
12 rithmetic Logic Unit (LU) inary dder/subtractor Op: Control Signal (Operation) Op= à S = x + y Op=1 à S = x y Op x 3 x 2 x 1 x 3 y 2 y 1 y 3 y 2 y 1 y C y inary dder S 3 S 2 S 1 S C S 3 S 2 S 1 S
13 rithmetic Logic Unit (LU) LU may contain multiple operation units Floating point unit S i g n E x p o n e n t S i g n i f i c a n d S i g n E x p o n e n t S i g n i f i c a n d S t a r t Exponents dder 1. C o m p a r e t h e e x p o n e n t s o f t h e t w o n u m b e r s. S h i f t t h e s m a l l e r n u m b e r t o t h e r i g h t u n t i l i t s e x p o n e n t w o u ld m a t c h t h e la r g e r e x p o n e n t E x p o n e n t d i f f e r e n c e 2. d d t h e s ig n if ic a n d s N o r m a liz e t h e s u m, e i t h e r s h i f t i n g r ig h t a n d in c r e m e n t in g t h e e x p o n e n t o r s h if t in g le f t a n d d e c r e m e n t in g t h e e x p o n e n t Control S h i f t r i g h t Significands dder O v e r f l o w o r u n d e r f lo w? Y e s N o E x c e p t i o n 1 I n c r e m e n t o r d e c r e m e n t 1 S h i f t l e f t o r r i g h t 4. R o u n d t h e s i g n i f i c a n d t o t h e a p p r o p r i a t e n u m b e r o f b i t s N o S t i l l n o r m a l i z e d? R o u n d i n g h a r d w a r e Y e s S i g n E x p o n e n t S i g n i f i c a n d D o n e
14 rithmetic Logic Unit (LU) LU may contain multiple operation units Comparator unit Magnitude Comparator < = > x + = x + = x + = x + = ) ( x x x x = = ) ( x x x x x x = > ) ( x x x x x x = <
15 rithmetic Logic Unit (LU) LU may contain multiple operation units Comparator unit x 3 3 Magnitude Comparator 2 x x 1 (<) < = > 1 x (>) (=)
16 rithmetic Logic Unit (LU) LU may contain multiple operation units Comparator unit x 7 x 6 x 5 x 4 y7 y 6 y 5 y 4 x 3 x 2 x 1 x y3 y 2 y 1 y I (>) I (=) I (<) Magnitude Comparator < = > I (>) I (=) I (<) Magnitude Comparator < = > < = >
17 rithmetic Logic Unit (LU) n n slt add sub fp cmp mlt Control multiplexer S n
18 rithmetic Logic Unit (LU) rithmetic circuits is built in a hierarchical fashion Input: data and operation to perform Output: result of operation and status information LU Control 4 32 LU 32 Zero Result Overflow 32 CarryOut
19 rithmetic Logic Unit (LU) Operation Examples LU control lines Function LU Control 4 ND 1 OR 1 DD 11 SU 32 LU 32 Zero Result Overflow 111 SLT 11 NOR 32 CarryOut
20 Register File Register D D 1 D 2... D n-1 En Clk ff ff ff... ff Q Q 1 Q 2... Q n-1
21 Register D D 1 D 2... D n-1 Register File En Clk ff Q ff Q 1 ff Q ff Q n-1 5 ws clk Register File wd rd1 rd rs1 5 rs2 5 reg we reg 1 1 reg 31
22 Register D D 1 D 2... D n-1 En Clk ff Q ff Q 1 ff Q Register File ff Q n-1 Register File Module Clock WE Register File we ws clk wd rd1 rd reg reg 1 reg 31 rs1 5 rs2 5 1 ReadSel1 ReadSel2 WriteSel WriteData rs1 rs2 ws wd we Register file 2R+1W rd1 rd2 ReadData1 ReadData2
23 Register File - MIPS Support 5 Read register number 1 read data Read register number 2 5 Write register Register file 32 Write data read data 2 32 Write
24 Computer Organization v1 Recall our second view of computer organization RegWrite clk inst<25:21> inst<2:16> inst<15:11> inst<5:> we rs1 rs2 rd1 ws wd rd2 GPRs LU Control LU Instruction Processor Data transfer ddress 2 Data Memory
25 MIPS Instructions There 3 types of instruction in MIPS 1. R-Type I-Type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt Immediate op rs rt/funct Displacement 3. J-Type op target
26 There 3 types of instruction in MIPS 1. R-Type add rd, rs, rt MIPS Instructions op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits LU Control Instruction rs rt rd read register 1 Read register 2 Write register Write data Register file Write read data 1 read data LU CarryOut Zero Overflow
27 There 3 types of instruction in MIPS 2. I-Type MIPS Instructions op rs rt Immediate Instruction lw rt, index(rs) rs rt rt Write Data Immediate op Read Reg. 1 Read Reg. 2 Registers Write Reg. 16 RegWrite Read Data 1 Read Data 2 rs rt/funct Displacement Sign Extend 32 LU Control LU zero ddress Data Memory Write Data MemWrite MemRead Read Data
28 There 3 types of instruction in MIPS 2. I-Type MIPS Instructions op rs rt Immediate Instruction beq rs, rt, displ rs rt rt op Read Reg. 1 Read Reg. 2 Registers Write Reg. Write Data RegWrite Read Data 1 Read Data 2 rs rt/funct Displacement PC+4 LU LU Control zero Shift left 2 DD To ranch Control Logic ranch Target ddress Immediate 16 Sign Extend 32
29 There 3 types of instruction in MIPS 3. J-Type MIPS Instructions op target j label PC+4[31-28] Instr[25-] Shift 26 left Jump Target ddress rs rt Instruction rt
30 LU Operation LU operation is based on instruction type and function code Performs subtraction for branches (beq) Performs no operation for jumps Performs the operation is specified by the function field for R-type instructions LU Control unit will have the following inputs: 2-bit control field called LUOp 6-bit function field
31 LU Operation Instruction opcode Instruction operation LUop Funct field Desired LU action LU Control LW Load word xxxxxx add 1 SW Store word xxxxxx add 1 EQ ranch equal 1 xxxxxx subtract 11 R-type DD 1 1 add 1 R-type SU 1 11 subtract 11 R-type ND 1 11 and R-type OR or 1 R-type SLT slt 111
32 Class fter Exam Central Processing Unit (CPU) Organization
Computer Engineering Department. CC 311- Computer Architecture. Chapter 4. The Processor: Datapath and Control. Single Cycle
Computer Engineering Department CC 311- Computer Architecture Chapter 4 The Processor: Datapath and Control Single Cycle Introduction The 5 classic components of a computer Processor Input Control Memory
More informationCPU DESIGN The Single-Cycle Implementation
CSE 202 Computer Organization CPU DESIGN The Single-Cycle Implementation Shakil M. Khan (adapted from Prof. H. Roumani) Dept of CS & Eng, York University Sequential vs. Combinational Circuits Digital circuits
More informationECE 2300 Digital Logic & Computer Organization
ECE 2300 Digital Logic & Computer Organization pring 201 More inary rithmetic LU 1 nnouncements Lab 4 prelab () due tomorrow Lab 5 to be released tonight 2 Example: Fixed ize 2 C ddition White stone =
More informationProcessor Design & ALU Design
3/8/2 Processor Design A. Sahu CSE, IIT Guwahati Please be updated with http://jatinga.iitg.ernet.in/~asahu/c22/ Outline Components of CPU Register, Multiplexor, Decoder, / Adder, substractor, Varity of
More informationControl. Control. the ALU. ALU control signals 11/4/14. Next: control. We built the instrument. Now we read music and play it...
// CS 2, Fall 2! CS 2, Fall 2! We built the instrument. Now we read music and play it... A simple implementa/on uc/on uct r r 2 Write r Src Src Extend 6 Mem Next: path 7-2 CS 2, Fall 2! signals CS 2, Fall
More informationProject Two RISC Processor Implementation ECE 485
Project Two RISC Processor Implementation ECE 485 Chenqi Bao Peter Chinetti November 6, 2013 Instructor: Professor Borkar 1 Statement of Problem This project requires the design and test of a RISC processor
More informationArithmetic and Logic Unit First Part
Arithmetic and Logic Unit First Part Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras ALU1-1 Typical
More informationReview: Single-Cycle Processor. Limits on cycle time
Review: Single-Cycle Processor Jump 3:26 5: MemtoReg Control Unit LUControl 2: Op Funct LUSrc RegDst PCJump PC 4 uction + PCPlus4 25:2 2:6 2:6 5: 5: 2 3 WriteReg 4: Src Src LU Zero LUResult Write + PC
More informationTEST 1 REVIEW. Lectures 1-5
TEST 1 REVIEW Lectures 1-5 REVIEW Test 1 will cover lectures 1-5. There are 10 questions in total with the last being a bonus question. The questions take the form of short answers (where you are expected
More informationSpiral 1 / Unit 3
-3. Spiral / Unit 3 Minterm and Maxterms Canonical Sums and Products 2- and 3-Variable Boolean Algebra Theorems DeMorgan's Theorem Function Synthesis use Canonical Sums/Products -3.2 Outcomes I know the
More informationOverview. Arithmetic circuits. Binary half adder. Binary full adder. Last lecture PLDs ROMs Tristates Design examples
Overview rithmetic circuits Last lecture PLDs ROMs Tristates Design examples Today dders Ripple-carry Carry-lookahead Carry-select The conclusion of combinational logic!!! General-purpose building blocks
More informationBuilding a Computer. Quiz #2 on 10/31, open book and notes. (This is the last lecture covered) I wonder where this goes? L16- Building a Computer 1
Building a Computer I wonder where this goes? B LU MIPS Kit Quiz # on /3, open book and notes (This is the last lecture covered) Comp 4 Fall 7 /4/7 L6- Building a Computer THIS IS IT! Motivating Force
More informationCMSC 313 Lecture 18 Midterm Exam returned Assign Homework 3 Circuits for Addition Digital Logic Components Programmable Logic Arrays
CMSC 33 Lecture 8 Midterm Exam returned ssign Homework 3 Circuits for ddition Digital Logic Components Programmable Logic rrays UMC, CMSC33, Richard Chang Half dder Inputs: and Outputs:
More informationModule 2. Basic Digital Building Blocks. Binary Arithmetic & Arithmetic Circuits Comparators, Decoders, Encoders, Multiplexors Flip-Flops
Module 2 asic Digital uilding locks Lecturer: Dr. Yongsheng Gao Office: Tech 3.25 Email: Web: Structure: Textbook: yongsheng.gao@griffith.edu.au maxwell.me.gu.edu.au 6 lecturers 1 tutorial 1 laboratory
More informationLecture 3, Performance
Lecture 3, Performance Repeating some definitions: CPI Clocks Per Instruction MHz megahertz, millions of cycles per second MIPS Millions of Instructions Per Second = MHz / CPI MOPS Millions of Operations
More informationComputer Architecture. ECE 361 Lecture 5: The Design Process & ALU Design. 361 design.1
Computer Architecture ECE 361 Lecture 5: The Design Process & Design 361 design.1 Quick Review of Last Lecture 361 design.2 MIPS ISA Design Objectives and Implications Support general OS and C- style language
More informationCPS 104 Computer Organization and Programming Lecture 11: Gates, Buses, Latches. Robert Wagner
CPS 4 Computer Organization and Programming Lecture : Gates, Buses, Latches. Robert Wagner CPS4 GBL. RW Fall 2 Overview of Today s Lecture: The MIPS ALU Shifter The Tristate driver Bus Interconnections
More informationCMP 334: Seventh Class
CMP 334: Seventh Class Performance HW 5 solution Averages and weighted averages (review) Amdahl's law Ripple-carry adder circuits Binary addition Half-adder circuits Full-adder circuits Subtraction, negative
More informationLecture 3, Performance
Repeating some definitions: Lecture 3, Performance CPI MHz MIPS MOPS Clocks Per Instruction megahertz, millions of cycles per second Millions of Instructions Per Second = MHz / CPI Millions of Operations
More informationImplementing the Controller. Harvard-Style Datapath for DLX
6.823, L6--1 Implementing the Controller Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 6.823, L6--2 Harvard-Style Datapath for DLX Src1 ( j / ~j ) Src2 ( R / RInd) RegWrite MemWrite
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing
More informationUNIT 8A Computer Circuitry: Layers of Abstraction. Boolean Logic & Truth Tables
UNIT 8 Computer Circuitry: Layers of bstraction 1 oolean Logic & Truth Tables Computer circuitry works based on oolean logic: operations on true (1) and false (0) values. ( ND ) (Ruby: && ) 0 0 0 0 0 1
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance
More informationOutcomes. Spiral 1 / Unit 2. Boolean Algebra BOOLEAN ALGEBRA INTRO. Basic Boolean Algebra Logic Functions Decoders Multiplexers
-2. -2.2 piral / Unit 2 Basic Boolean Algebra Logic Functions Decoders Multipleers Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name eamples of each.
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 19: Adder Design [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN 411 L19
More informationCSE Computer Architecture I
Execution Sequence Summary CSE 30321 Computer Architecture I Lecture 17 - Multi Cycle Control Michael Niemier Department of Computer Science and Engineering Step name Instruction fetch Instruction decode/register
More informationChapter 7: Digital Components. Oregon State University School of Electrical Engineering and Computer Science. Review basic digital design concepts:
hapter 7: igital omponents Prof. en Lee Oregon tate University chool of Electrical Engineering and omputer cience hapter Goals Review basic digital design concepts: esigning basic digital components using
More informationPipelining. Traditional Execution. CS 365 Lecture 12 Prof. Yih Huang. add ld beq CS CS 365 2
Pipelining CS 365 Lecture 12 Prof. Yih Huang CS 365 1 Traditional Execution 1 2 3 4 1 2 3 4 5 1 2 3 add ld beq CS 365 2 1 Pipelined Execution 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5
More informationCHAPTER log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C * 9-4.* (Errata: Delete 1 after problem number) 9-5.
CHPTER 9 2008 Pearson Education, Inc. 9-. log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C 7 Z = F 7 + F 6 + F 5 + F 4 + F 3 + F 2 + F + F 0 N = F 7 9-3.* = S + S = S + S S S S0 C in C 0 dder
More informationReview. Combined Datapath
Review Topics:. A single cycle implementation 2. State Diagrams. A mltiple cycle implementation COSC 22: Compter Organization Instrctor: Dr. Amir Asif Department of Compter Science York University Handot
More informationArithmetic Circuits How to add and subtract using combinational logic Setting flags Adding faster
rithmetic Circuits Didn t I learn how to do addition in second grade? UNC courses aren t what they used to be... 01011 +00101 10000 Finally; time to build some serious functional blocks We ll need a lot
More informationVerilog HDL:Digital Design and Modeling. Chapter 11. Additional Design Examples. Additional Figures
Chapter Additional Design Examples Verilog HDL:Digital Design and Modeling Chapter Additional Design Examples Additional Figures Chapter Additional Design Examples 2 Page 62 a b y y 2 y 3 c d e f Figure
More informationCPSC 3300 Spring 2017 Exam 2
CPSC 3300 Spring 2017 Exam 2 Name: 1. Matching. Write the correct term from the list into each blank. (2 pts. each) structural hazard EPIC forwarding precise exception hardwired load-use data hazard VLIW
More informationLecture 13: Sequential Circuits, FSM
Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines 1 Clocks A microprocessor is composed of many different circuits that are operating simultaneously if each
More informationFundamentals of Computer Systems
Fundamentals of omputer Systems ombinational Logic Stephen. Edwards olumbia University Fall 2012 Encoders and Decoders Decoders Input: n-bit binary number Output: 1-of-2 n one-hot code 2-to-4 in out 00
More informationArithmetic Circuits Didn t I learn how to do addition in the second grade? UNC courses aren t what they used to be...
rithmetic Circuits Didn t I learn how to do addition in the second grade? UNC courses aren t what they used to be... + Finally; time to build some serious functional blocks We ll need a lot of boxes The
More informationSolutions for Appendix C Exercises
C Solutions for Appix C Exercises 1 Solutions for Appix C Exercises C.1 A B A B A + B A B A B A + B 0 0 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 C.2 Here is the first equation: E = ((
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEMORY INPUT-OUTPUT CONTROL DATAPATH
More information[2] Predicting the direction of a branch is not enough. What else is necessary?
[2] What are the two main ways to define performance? [2] Predicting the direction of a branch is not enough. What else is necessary? [2] The power consumed by a chip has increased over time, but the clock
More informationChapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>
Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Simple Processor CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Digital
More informationLecture 13: Sequential Circuits, FSM
Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines Reminder: midterm on Tue 2/28 will cover Chapters 1-3, App A, B if you understand all slides, assignments,
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationComputer Architecture. ESE 345 Computer Architecture. Design Process. CA: Design process
Computer Architecture ESE 345 Computer Architecture Design Process 1 The Design Process "To Design Is To Represent" Design activity yields description/representation of an object -- Traditional craftsman
More informationECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks
ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational
More informationChapter 2. Review of Digital Systems Design
x 2-4 = 42.625. Chapter 2 Review of Digital Systems Design Numbering Systems Decimal number may be expressed as powers of 10. For example, consider a six digit decimal number 987654, which can be represented
More information3. (2) What is the difference between fixed and hybrid instructions?
1. (2 pts) What is a "balanced" pipeline? 2. (2 pts) What are the two main ways to define performance? 3. (2) What is the difference between fixed and hybrid instructions? 4. (2 pts) Clock rates have grown
More informationChapter 5 Arithmetic Circuits
Chapter 5 Arithmetic Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 11, 2016 Table of Contents 1 Iterative Designs 2 Adders 3 High-Speed
More information[2] Predicting the direction of a branch is not enough. What else is necessary?
[2] When we talk about the number of operands in an instruction (a 1-operand or a 2-operand instruction, for example), what do we mean? [2] What are the two main ways to define performance? [2] Predicting
More information61C In the News. Processor Design: 5 steps
www.eetimes.com/electronics-news/23235/thailand-floods-take-toll-on--makers The Thai floods have already claimed the lives of hundreds of pele, with tens of thousands more having had to flee their homes
More informationUNIVERSITY OF WISCONSIN MADISON
CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON Prof. Gurindar Sohi TAs: Minsub Shin, Lisa Ossian, Sujith Surendran Midterm Examination 2 In Class (50 minutes) Friday,
More informationReview. EECS Components and Design Techniques for Digital Systems. Lec 18 Arithmetic II (Multiplication) Computer Number Systems
Review EE 5 - omponents and Design Techniques for Digital ystems Lec 8 rithmetic II (Multiplication) David uller Electrical Engineering and omputer ciences University of alifornia, Berkeley http://www.eecs.berkeley.edu/~culler
More informationArithmetic Building Blocks
rithmetic uilding locks Datapath elements dder design Static adder Dynamic adder Multiplier design rray multipliers Shifters, Parity circuits ECE 261 Krish Chakrabarty 1 Generic Digital Processor Input-Output
More informationCS 140 Lecture 14 Standard Combinational Modules
CS 14 Lecture 14 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego Some slides from Harris and Harris 1 Part III. Standard Modules A. Interconnect B. Operators. Adders Multiplier
More informationVLSI Design. [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1
VLSI Design Adder Design [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] ECE 4121 VLSI DEsign.1 Major Components of a Computer Processor Devices Control Memory Input Datapath
More informationDesign of Digital Circuits Lecture 14: Microprogramming. Prof. Onur Mutlu ETH Zurich Spring April 2017
Design of Digital Circuits Lecture 4: Microprogramming Prof. Onur Mutlu ETH Zurich Spring 27 7 April 27 Agenda for Today & Next Few Lectures! Single-cycle Microarchitectures! Multi-cycle and Microprogrammed
More informationCSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing
CSE4: Components and Design Techniques for Digital Systems Decoders, adders, comparators, multipliers and other ALU elements Tajana Simunic Rosing Mux, Demux Encoder, Decoder 2 Transmission Gate: Mux/Tristate
More informationBit-Sliced Design. EECS 141 F01 Arithmetic Circuits. A Generic Digital Processor. Full-Adder. The Binary Adder
it-liced Design Control EEC 141 F01 rithmetic Circuits Data-In Register dder hifter it 3 it 2 it 1 it 0 Data-Out Tile identical processing elements Generic Digital Processor Full-dder MEMORY Cin Full adder
More informationL07-L09 recap: Fundamental lesson(s)!
L7-L9 recap: Fundamental lesson(s)! Over the next 3 lectures (using the IPS ISA as context) I ll explain:! How functions are treated and processed in assembly! How system calls are enabled in assembly!
More informationHw 6 due Thursday, Nov 3, 5pm No lab this week
EE141 Fall 2005 Lecture 18 dders nnouncements Hw 6 due Thursday, Nov 3, 5pm No lab this week Midterm 2 Review: Tue Nov 8, North Gate Hall, Room 105, 6:30-8:30pm Exam: Thu Nov 10, Morgan, Room 101, 6:30-8:00pm
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationCOVER SHEET: Problem#: Points
EEL 4712 Midterm 3 Spring 2017 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)
More informationAdders allow computers to add numbers 2-bit ripple-carry adder
Lecture 12 Logistics HW was due yesterday HW5 was out yesterday (due next Wednesday) Feedback: thank you! Things to work on: ig picture, ook chapters, Exam comments Last lecture dders Today Clarification
More informationLecture: Pipelining Basics
Lecture: Pipelining Basics Topics: Performance equations wrap-up, Basic pipelining implementation Video 1: What is pipelining? Video 2: Clocks and latches Video 3: An example 5-stage pipeline Video 4:
More informationEE 109 Final Don t Make the Same Mistake
EE 9 Final Don t Make the ame Mistake No calculators are allowed. how all your work to get full credit. Note: The following are all INCORRECT answers meant to highlight common misunderstandings! Try to
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEM ORY INPUT-OUTPUT CONTROL DATAPATH
More informationAppendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs
Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR
More informationARITHMETIC COMBINATIONAL MODULES AND NETWORKS
ARITHMETIC COMBINATIONAL MODULES AND NETWORKS 1 SPECIFICATION OF ADDER MODULES FOR POSITIVE INTEGERS HALF-ADDER AND FULL-ADDER MODULES CARRY-RIPPLE AND CARRY-LOOKAHEAD ADDER MODULES NETWORKS OF ADDER MODULES
More informationDigital Integrated Circuits A Design Perspective. Arithmetic Circuits
Digital Integrated Circuits Design Perspective rithmetic Circuits Reference: Digital Integrated Circuits, 2nd edition, Jan M. Rabaey, nantha Chandrakasan and orivoje Nikolic Disclaimer: slides adapted
More information1. (2 )Clock rates have grown by a factor of 1000 while power consumed has only grown by a factor of 30. How was this accomplished?
1. (2 )Clock rates have grown by a factor of 1000 while power consumed has only grown by a factor of 30. How was this accomplished? 2. (2 )What are the two main ways to define performance? 3. (2 )What
More informationDesign. Dr. A. Sahu. Indian Institute of Technology Guwahati
CS222: Processor Design: Multi Cycle Design Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati Mid Semester Exam Multi Cycle design Outline Clock periods in single cycle and
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING ELURU DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER
SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU 534 007 DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DIGITAL
More informationCombinational Logic. By : Ali Mustafa
Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output
More informationUNIT III Design of Combinational Logic Circuits. Department of Computer Science SRM UNIVERSITY
UNIT III Design of ombinational Logic ircuits Department of omputer Science SRM UNIVERSITY Introduction to ombinational ircuits Logic circuits for digital systems may be ombinational Sequential combinational
More information8. Design Tradeoffs x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS
8. Design Tradeoffs 6.004x Computation Structures Part 1 Digital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L08: Design Tradeoffs, Slide #1 There are a large number of implementations
More informationEXPERIMENT Bit Binary Sequential Multiplier
12.1 Objectives EXPERIMENT 12 12. -Bit Binary Sequential Multiplier Introduction of large digital system design, i.e. data path and control path. To apply the above concepts to the design of a sequential
More informationDesign of Sequential Circuits
Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable
More information8. Design Tradeoffs x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS
8. Design Tradeoffs 6.004x Computation Structures Part 1 Digital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L08: Design Tradeoffs, Slide #1 There are a large number of implementations
More informationUNSIGNED BINARY NUMBERS DIGITAL ELECTRONICS SYSTEM DESIGN WHAT ABOUT NEGATIVE NUMBERS? BINARY ADDITION 11/9/2018
DIGITAL ELECTRONICS SYSTEM DESIGN LL 2018 PROFS. IRIS BAHAR & ROD BERESFORD NOVEMBER 9, 2018 LECTURE 19: BINARY ADDITION, UNSIGNED BINARY NUMBERS For the binary number b n-1 b n-2 b 1 b 0. b -1 b -2 b
More informationSimple Instruction-Pipelining. Pipelined Harvard Datapath
6.823, L8--1 Simple ruction-pipelining Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Pipelined Harvard path 6.823, L8--2. I fetch decode & eg-fetch execute memory Clock period
More information4. (3) What do we mean when we say something is an N-operand machine?
1. (2) What are the two main ways to define performance? 2. (2) When dealing with control hazards, a prediction is not enough - what else is necessary in order to eliminate stalls? 3. (3) What is an "unbalanced"
More informationEE 209 Logic Cumulative Exam Name:
EE 209 Logic Cumulative Exam Name: 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines: true / false b.) An 8-to-1 mux and no other logi can be
More informationChapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.
Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Multiplication CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev HW
More informationNumbers and Arithmetic
Numbers and Arithmetic See: P&H Chapter 2.4 2.6, 3.2, C.5 C.6 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register file alu
More informationLogic. Basic Logic Functions. Switches in series (AND) Truth Tables. Switches in Parallel (OR) Alternative view for OR
TOPIS: Logic Logic Expressions Logic Gates Simplifying Logic Expressions Sequential Logic (Logic with a Memory) George oole (85-864), English mathematician, oolean logic used in digital computers since
More informationCPU DESIGN The Single-Cycle Implementation
22 ompter Organization Seqential vs. ombinational ircits Digital circits can be classified into two categories: DESIGN The Single-ycle Implementation. ombinational ircits: m, 2. Seqential ircits: flip-flops,
More informationSimple Instruction-Pipelining. Pipelined Harvard Datapath
6.823, L8--1 Simple ruction-pipelining Updated March 6, 2000 Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Pipelined Harvard path 6.823, L8--2. fetch decode & eg-fetch execute
More informationLecture 12: Adders, Sequential Circuits
Lecture 12: Adders, Sequential Circuits Today s topics: Carry-lookahead adder Clocks, latches, sequential circuits 1 Incorporating beq Perform a b and confirm that the result is all zero s Source: H&P
More informationCS 52 Computer rchitecture and Engineering Lecture 4 - Pipelining Krste sanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste! http://inst.eecs.berkeley.edu/~cs52!
More informationA crash course in Digital Logic
crash course in Digital Logic Computer rchitecture 1DT016 distance Fall 2017 http://xyx.se/1dt016/index.php Per Foyer Mail: per.foyer@it.uu.se Per.Foyer@it.uu.se 2017 1 We start from here Gates Flip-flops
More informationOutcomes. Spiral 1 / Unit 3. The Problem SYNTHESIZING LOGIC FUNCTIONS
-3. -3.2 Outcomes Spiral / Unit 3 Minterm and Materms Canonical Sums and Products 2 and 3 Variable oolean lgebra Theorems emorgan's Theorem unction Snthesis use Canonical Sums/Products Mark Redekopp I
More informationChapter 5. Digital systems. 5.1 Boolean algebra Negation, conjunction and disjunction
Chapter 5 igital systems digital system is any machine that processes information encoded in the form of digits. Modern digital systems use binary digits, encoded as voltage levels. Two voltage levels,
More informationDigital Logic: Boolean Algebra and Gates. Textbook Chapter 3
Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible
More informationHardware Design I Chap. 4 Representative combinational logic
Hardware Design I Chap. 4 Representative combinational logic E-mail: shimada@is.naist.jp Already optimized circuits There are many optimized circuits which are well used You can reduce your design workload
More informationEnrico Nardelli Logic Circuits and Computer Architecture
Enrico Nardelli Logic Circuits and Computer Architecture Appendix B The design of VS0: a very simple CPU Rev. 1.4 (2009-10) by Enrico Nardelli B - 1 Instruction set Just 4 instructions LOAD M - Copy into
More informationSample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
More informationBasic Computer Organization and Design Part 3/3
Basic Computer Organization and Design Part 3/3 Adapted by Dr. Adel Ammar Computer Organization Interrupt Initiated Input/Output Open communication only when some data has to be passed --> interrupt. The
More informationECE/Comp Sci 352 Digital Systems Fundamentals. Charles R. Kime Section 2 Fall Logic and Computer Design Fundamentals
University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Charles R. Kime Section 2 Fall 2001 Lecture 5 Registers & Counters Part 2 Charles Kime Counters Counters are sequential circuits
More informationFundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
More information