Designing Single-Cycle MIPS Processor

Transcription

1 CSE 32: Introdction to Compter Architectre Designing Single-Cycle IPS Processor Presentation G Stdy:.-. Gojko Babić 2/9/28 Introdction We're now ready to look at an implementation of the system that incldes IPS processor and. The design will inclde spport for eection of only: -reference instrctions: lw & sw, arithmetic-logical instrctions: add, sb, and, or, slt & nor, control flow instrctions: beq & j, eception handling: illegal instrction & overflow. Bt that design will provide s with principles, so many more instrctions cold be easily added sch as: add, lb, lb, li, addi, addi, slt, slti, andi, ori, or, ori, jal, jr, jalr, bne, beqz, bgtz, bltz, nop, mfhi, mflo, mfepc, mfco, lwc, swc, etc. g. babic Presentation G 2

2 Single Cycle Design We shall first design a simpler processor that eectes each instrction in only one clock cycle time. This is not efficient from performance point of view, since: a clock cycle time (i.e. clock rate) mst be chosen sch that the longest instrction can be eected in one clock cycle and that makes shorter instrctions eecte in one nnecessarily long cycle. itionally, no resorce in the design may be sed more than once per instrction, ths some resorces will be dplicated. Ths, the singe cycle design will reqire: two memories (instrction and ), two additional adders. g. babic Presentation G 3 Elements for path Design a. Program conter ALU control res lt overflow ress em 6 Sign c. ALU em g. Sign-etension nit e. nit Register nmbers Reg Sm d. er em= em = f. Shift Left 2 h. Shift left 2 b. Register File An edge triggered methodology g. babic Presentation G 2

3 Abstract / Simplified View Figre. Use the program conter () to spply instrction, Get the instrction from, s and se the instrction opcode to decide what to do is incremented by most instrctions, and + offset by branches Jmp instrctions change differently (not shown). g. babic Presentation G 5 Incrementing & Fetching A d d P C a d d r e s s In s tr c tio n In s tr c tio n m e m o r y Figre.6 with addition in red g. babic Presentation G 6 3

4 path for R-type s R e g W r ite I 25-2 ALU control In s tr c tio n I 2-6 Z e r o I 5- R e g is t e r s W r ite A L U A L U re s lt W r ite 2 d a t a add = sb = slt = 2 R-type rs rt rd fnct and = 36 or = 37 g. babic Presentation G nor = 39 7 Complete path for R-type s Based on contents of op-code and fnct fields, Control Unit sets ALU control appropriately and asserts Reg, i.e. Reg =. R e g W r ite I 25-2 I 2-6 re g is te r re g is te r 2 d a ta ALU control Z e r o clock I 5- R e g is t e r s W r ite re g is te r d a ta 2 W r ite A L U A L U re s lt d a t a g. babic Presentation G 8

5 path for LW and SW s sw or lw opcode rs rt offset R e g W r ite em In strc tion I 25-2 I 2-6 I ALU control ress em I 5-6 Sign em Control Unit sets: ALU control = (add) for calclation for both lw and sw em=, em= and Reg= for sw em=, em= and Reg= for lw g. babic Presentation G 9 path for R-type, LW & SW s Reg em In str ction em = em = rs rt rd registe r registe r 2 6 Sign offset A L U control ress em emtoreg Let s determine setting of control lines for R-type, lw & sw instrctions. g. babic Presentation G 5

6 path for BEQ beq rs rt offset Branch target = [] + + offset + from instrction path Sm Branch target Shift left 2 Instrc tio n rs rt 2 A L U control ALU To branch control logic Reg offset 6 Sign Figre.9 with additions in red g. babic Presentation G path for R-type, LW, SW & BEQ branch Src Reg Shift left 2 ALU em clock [3 ] em= em= [25 2] rs [2 6] rt [5 ] rd [5 ] offset 2 6 Sign ress em emtoreg ALU control Figre.5 with additions in red g. babic Presentation G 2 6

7 Control Unit and path ALU Branch Shift left 2 Src em [3 26] opcode Control emtoreg ALUOp em [3 ] em= em= [25 2] [2 6] rt [5 ] rd [5 ] rs Reg anded 2 6 offset Sign ALU control ress anded [5 ] fnct Figre.7 with additions in red g. babic Presentation G 3 Trth Table for (ain) Control Unit Inpt Otpt Figre.8 emto- Reg em em Op-code Reg Branch ALUOp ALUp R-type lw sw beq d d d d d d ALUOp[-] = signal to ALU Control nit for ALU to perform add fnction, i.e. set Ainvert =, Binvert= and Operation= ALUOp[-] = signal to ALU Control nit for ALU to perform sbtract fnction, i.e. set Ainvert =, Binvert= and Operation= ALUOp[-] = signal to ALU Control nit to look at bits I [5-] and based on its pattern to set Ainvert, Binvert and Operation so that ALU performs appropriate fnction, i.e. add, sb, slt, and, or & nor g. babic Presentation G 7

8 Trth Table of ALU Control Unit Inpt Otpt ALUOp Fnct field ALU ALUOp ALUOp F5 F F3 F2 F F Control d d d d d d d d d d d d add sb add sb and or slt nor Ainvert Bivert Operation g. babic Presentation G 5 Design of (ain) Control Unit Op-code bits emto- Reg em em Reg Branch ALUOp ALUp d d d d d d Inpts Op5 Op =Op 5 Op Op 3 Op 2 Op Op Op3 Op2 Op Op = Op 5 Op Op 3 Op 2 Op Op +Op 5 Op Op 3 Op 2 Op Op R-format Iw sw beq Otpts emtoreg Reg em em Branch ALUOp ALUOpO g. babic Presentation G 6 8

9 path for R-type, LW, SW, BEQ & J j jmp_target 3-28 jmp_target 2 zeros [3-28] [25 ] Shift Jmp [3 ] left [3 28] Jmp Branch shift left 2 ALU [3 26] em Control emtoreg ALUOp em Reg [3 ] [25 2] [2 6] [5 ] 2 ress Figre.2 with correction in red [5 ] 6 Sign [5 ] ALU control g. babic Presentation G 7 Design of Control Unit (J inclded) Op-code bits emto- Reg Reg em em Branch ALUOp ALUp d d d d d d J d d d d d d d Jmp =Op 5 Op Op 3 Op 2 Op Op Inpts Op5 Op Op3 Op2 Op Op Jmp R-format Iw sw beq Jmp No changes in ALU Control nit emtoreg Reg em em Branch ALUOp ALUOpO g. babic Presentation G 8 9

10 Design of ALU Control Unit Withot NOR Inpt Otpt ALUOp Fnct field ALU ALUOp ALUOp F5 F F3 F2 F F Control d d d d d d d d d d d d ALUOP ALUOP add sb add sb and or slt Bivert Operation F5 F F3 F2 ALU Control Lines (Binvert & Operation) F F g. babic 9 Cycle Time Calclation Let s assme that the only delays introdced are by the following tasks: emory access (read and write time = 3 nsec) Register file access (read and write time = nsec) ALU to perform fnction (= 2 nsec) Under those assmption here are instrction eection times: Instr Reg ALU Reg fetch read oper write Total R-type = 7 nsec lw = nsec sw = 9 nsec branch = 6 nsec jmp 3 = 3 nsec Ths a clock cycle time has to be nsec, and clock rate = / nsec = Hz g. babic Presentation G 2

11 Single Cycle Processor: Conclsion Single Cycle Problems: what if we had a more complicated instrction like floating point? a clock cycle wold be mch longer, ths for shorter and more often sed instrctions, sch as add & lw, wastefl of time. One Soltion: se a smaller cycle time, and have different instrctions take different nmbers of cycles. And that is a mlti-cycle processor. g. babic Presentation G 2