Digital Design. Register Transfer Specification And Design

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1 Principles Of Digital Design Chapter 8 Register Transfer Specification And Design

2 Chapter preview Boolean algebra 3 Logic gates and flip-flops 3 Finite-state machine 6 Logic design techniques 4 Sequential design techniques 6 Binary system and data representation 2 Combinational components 5 Storage components 7 Generalized finite-state machines 8 Register-transfer design 8 Processor components 9 2

3 Register-transfer transfer design Each standard or custom IC consists of one or more datapaths and control units. To synthesize such IC we introduce the model of a FSM with a datapath (FSMD). We demonstrate synthesis algorithms for FSMD model, including component selection, resource sharing, pipelining and scheduling. 3

4 Example 7. 4

5 Design Model Control inputs Control unit Control signals Status signals Datapath inputs Datapath Control inputs Control outputs Datapath outputs High-level block diagram Datapath inputs D Q Control signals Control unit Nextstate logic. D Q. D Q State register. Output logic Status signals Register Control Datapath outputs outputs Register-transfer-level block diagram 5 RF ALU */ Register Mem Bu Bu Bus 3 Datapath

6 Ones-counter specification Data Mask Temp Ocount Start = Start = Done=; Data = Input Done=; Ocount = Done=; Mask = Done=; Temp = Data AND Mask Data = Done=; Ocount = Ocount + Temp Data = 6 Done=; Data = Data >> Done=; Output =Ocount

7 FSDM Definition In Chapter 6 we defined an FSM as a quintuple < S, I, O, f, h > where S is a set of states, I and O are the sets of input and output symbols: f : S I S, and h : S I O More precisely, I = A A2 Ak S = Q Q2 Qm O = Y Y2 Yn Where Ai, i k, is an input signal, Qi, i m is the flip-flop output and Yi, i n is an output signal. To define a FSMD, we define a set of variables V = V V2 Vq which defines the state of the datapath by defining the values of all variables in each state. = U U{ ( W ) W } { V V { p f }} = = = I= I I C D where IC = A A2 Ak as before and ID = B B2 Bp, O= O O C D Where OC = Y Y2 Yn as before and OD = Z Z2 Zr. 7

8 FSDM Definition With formal definition of expressions and relations over a set of variables we can simplify function f : ( S V ) I S V by separating it into two parts: fc and fd. The function fc defines the next state of the control unit fc : S IC STAT S while the function fd defines the values of datapath variables in the next state fd : S V ID V Also, and fd :={fdi : V ID V : { Vj =ej Vj V, ej Expr ( V ID )}} hc : S IC STAT OC hd : S V ID OD 8

9 FSMD specification of Ones-counter Next state Control Datapath Present Datapath Variables (Start. Data=) Output output State Done Outport Data Ocount Temp Mask Z s 3 s 6 s 7 s 7 s 7 s 3 s 3 s 3 s 3 s 6 s 6 s 6 s 6 Z Inport Z Data Z Data Ocount Z Data Ocount Data AND Mask Mask Z Data Ocount+Temp Mask Z Data>> Ocount Mask Ocount Data Ocount Next state Control Datapath Present (Start. Data=) Output output Data Variables State Done Outport Z Z Data = Inport s s s 3 s s 3 Z Ocount = s 3 Z Mask = Z Temp = Data AND Mask s 6 s 7 s 6 s 6 s 6 s 6 s 7 s 7 Z Ocount = Ocount + Temp Z Data = Data >> Ocount State and output table Present Next state State condition state Start = Start = Data = s 3 s 3 s 6 s 7 [ [ Data s 6 s 7 ] ] Control and Datapath actions condition actions Done = Data = Inport Ocount = Mask = Temp = Data AND Mask Ocount = Ocount + Temp [ Data = Data >> Done = Data = Inport ] State and output table with variable assignments 9 State-action table

10 Algorithmic-State State-Machine Graphic representation of FSMD model Equivalent to state-action table Similar to a flowchart used for program description

11 Name State box ASM Symbols Definition Example Decision Box Condition Box ASM Block

12 ASM rules Rule : The chart must define a unique next state for each state and set of conditions. Rule 2: Every path defined by the network of condition boxes must lead to another state. ASM block ASM block cond cond2 cond cond2 s 3 s 3 Undefined next state 2 Undefined exit path

13 ASM chart for Ones-counter (a) State-based (Moore) chart (b) Input-based (Mealy) chart 3

14 State-action action tables for Ones-counter State-based table Present State Q 2 Q Q Name s 3 Next state Condition Start =, Start =, Data LSR =, Data LSR =, Data, Data =, State s 3 4 Datapath actions condition Operations Done = Data = Inport Ocount = Ocount = Ocount + Data = Data >> Done = Output = Ocount = = + + = + + = = + + = + + = = + + = + + = = = + = + = = = = = = =

15 State-action action tables for Ones-counter Input-based table Present State Q Q Name s 3 [ [ Next state Condition State Start =, ] Start =, Data =, Data =, = = + = + = = + = + Datapath actions condition Operations Done = Data = Inport Ocount = Data LSR =, Ocount = Ocount + ] [ s 3 Data =, Data = Data >> Done = [ ] Output = Ocount [ ] ] = = = = + = + = = = = = = = 5

16 Logic schematics for Ones-counter D 2 = Q 2 (next) = Data LSB + S 3 + S 4 (Data ) = Q Q Data LSB + Q Q + Q 2 Q (Data ) D = Q (next) = + Data LSB + (Data ) = Q 2 Q Q + Q Q Data LSB + Q 2 Q (Data ) D = Q (next) = Start + Data LSB + (Data ) = Q 2 Q Q Start+Q Q Data LSB +Q 2 Q (Dara ) S = =Q 2 Q S = + = Q Q + Q 2 Q E = s 3 = Q Q Load = = Q 2 Q Q Done = Output enable = = Q 2 Q State-based version 6

17 Logic schematics for Ones-counter D = Q ( next ) = + = Q Q + Q Q D = Q ( next ) = Start + ( Data ) = Q Q Start + Q Q ( Data ) S = ( Data ) = Q Q ( Data ) S = + ( Data ) = Q Q + Q Q ( Data ) E = Data LSB = Q Q Data LSB Load = = Q Q Done = Output enable = s 3 = Q Q Input-based version 7

18 Register-transfer transfer synthesis Block diagram Register sharing a = In b = In 2 s 3 Start t = a t 2 = b x = max( t, t 2 ) y = min ( t, t 2 ) t 3 = x >> 3 t 4 = y >> t 5 = x t 3 Functional unit sharing Bus sharing t 6 = t 4 + t 5 s 6 t 7 = max ( t 6, x ) s 7 ASM Chart of Square-root approximation Done = Out = t 7 8

19 Resource usage in square-root root Block diagram a = In b = In 2 s 3 s 6 s 7 Start t = a t 2 = b x = max( t, t 2 ) y = min ( t, t 2 ) t 3 = x >> 3 t 4 = y >> t 5 = x t 3 t 6 = t 4 + t 5 t 7 = max ( t 6, x ) Done = Out = t 7 ASM Chart of Square-root approximation approximation max No. of operations 9 abs min >> - + a b t t 2 x y t 3 t 4 t 5 t 6 t 7 No. of live variables s 3 s Variable usage 3 Operation usage s 6 2 s 6 s 7 s 7 Max. no. of units 2 2

20 (a) Absolute value unit (version ) Simple library components b Sign bit Subtractor Sign bit b Subtractor b (b) Absolute value unit (version 2) a b b a b b a b Subtractor Subtractor Subtractor Sign bit Sign bit min/max control Sign bit (c) Min unit (d) Max unit (e) Min/Max unit a a>> (f) -bit right shifter (g) 3-bit right shifter (h) -bit/3-bit right shifter a Min(a,b) Adder a+b b Adder a Max(a,b) a a>>3 a-b b Shift control add/sub control min/max(a,b) (i) Adder (j) Subtractor (k) Adder/Subtractor >> a a a>>3/a>> Adder a+b/a-b >>3 b 2

21 Connectivity requirements Block diagram a = In b = In 2 abs a b t t 2 x y t 3 t 4 t 5 t 6 t 7 Start abs2 s 3 t = a t 2 = b x = max( t, t 2 ) y = min ( t, t 2 ) t 3 = x >> 3 t 4 = y >> min max >>3 >> t 5 = x t 3 - t 6 = t 4 + t 5 + s 6 t 7 = max ( t 6, x ) Connectivity table s 7 ASM Chart of Square-root approximation Done = Out = t 7 2

22 Register sharing (Variable merging) Grouping of variables with nonoverlaping lifetimes Each group shares one register Grouping reduces number of registers needed in the design Two algorithms: left-edge edge graph-partitioning partitioning 22

23 Left-edge edge algorithm 23

24 Register sharing by left-edge edge algorithm a b t t 2 x y t 3 t 4 t 5 t 6 t 7 s 3 s 6 Sorted list of variables s 7 R = {a, t, x, t7} R2 = {b, t2, y, t4, t6} R3 = {t2, t5 } Register assignments a = In b = In 2 s 3 Start t = a t 2 = b x = max( t, t 2 ) y = min ( t, t 2 ) t 3 = x >> 3 t 4 = y >> t 5 = x t 3 t 6 = t 4 + t 5 s 6 t 7 = max ( t 6, x ) s 7 Done = Out = t 7 Datapath schematic 24 ASM Chart

25 Merging variables with common sources and destination a c b d a, c b, d s i x = a + b s j y = c + d + + x y x, y Partial ASM Chart Datapath without register sharing Datapath with register sharing 25

26 Graph partitioning algorithm / (a) Initial compatibility graph Start Create compatibility graph Merge highest priority nodes Upgrade compatibility graph no All nodes incompatible yes Stop 26

27 Graph partitioning algorithm for SRA / (a) Initial compatibility grah a = In b = In 2 (b) Compatibility graph after merging t 3, t 5 and t 6 Start t = a t 2 = b x = max( t, t 2 ) y = min ( t, t 2 ) (c) Compatibility graph after merging t, x and t 7 s 3 t 3 = x >> 3 t 4 = y >> t 5 = x t 3 (d) Compatibility graph after merging t 2 and y s 6 t 6 = t 4 + t 5 t 7 = max ( t 6, x ) (e) Final compatibility graph 27 s 7 Done = Out = t 7 ASM Chart

28 Register assignment generated by the graph-partitioning partitioning algorithm R = [ a, t, x, t7 ] R2 =[b, t2, y, t3, t5, t6 ] R3= [ t4 ] Register assignments Datapath 28

29 Functional unit sharing (operator merging) Group non-concurrent operations Each group shares one functional unit Sharing reduces number of functional units Prioritized grouping by reducing connectivity Clustering algorithm used for grouping 29

30 Functional unit sharing Partial ASM Chart Non-shared design Shared design 3

31 Complex library components c c Operation absolute minimum c c Operation addition minimum maximum subtraction maximum Unit for computing minimum, maxmum and absolute value Unit for computing addition, subtraction, minimum and maximum c c Operation addition absolute c 2 c c Operation addition absolute subtraction subtraction minimum maximum Unit for computing addition, subtraction, and absolute value 3 Unit for computing addition, subtraction, minimum, maximum and absolute value

32 Operator merging for SRA implementation Compunoent AND Invert Logic Logic Unit a E-OR Adder Logic b (a) Compatibiltity graph min max + - Total (b) Cost table (c) Merging altermative Compunoent AND Unit Logic [ a /min] [ b /max/+/-] Invert E-OR Adder Logic Logic 2 2 ASM Chart (e) Merging altermative32 Total Compunoent AND Unit Logic (d) Cost table Invert E-OR Adder Logic Logic [ a /min/+] 2 [ b /max/+] 2 Total (f) Cost table

33 Datapath connectivity R R 2 R 3 [ abs/min] [ abs/max/+/- ] >> >>3 (a) Datapath schematic for unit allocation from figure 8.22 (c) R R 2 R 3 [ abs/min/+] [ abs/max/- ] >> >>3 ASM Chart (b) Datapath schematic for unit allocation from figure 8.22 (e) 33

34 Priorities in unit merging a, c b, d a, c b, d s i x = a + b s j y = c + d + - x, y +/- x, y (a) Partial ASM Chart (b) Design without merged units (c) Design with merged units 34

35 Unit merging for SRA datapath (a) Compatibility graph (b) Compatibility graph after merging of + and _ (c) Compatibility graph after merging of min, + and _ (d) Final graph partitions 35 ASM Chart

36 SRA datapath generated by prioritized partitioning AU R = [ a, t, x, t 7 ] = [ b / min / + / - ] R 2 = [ b, t 2, y, t 3, t 5, t 6 ] AU 2 = [ a / max /] R 3 = [ t 4 ] SH = [ >> ] SH 2 = [ >>3 ] (a) Register and functional unit allocation R R 2 R 3 [ abs/max] [ abs/min/+/- ] >> >>3 (b) Datapath schematic 36

37 Bus sharing ( connection merging ) Group connections that are not used concurrectly Each group forms a bus Connection merging reduces number of wires Clustering algorithm is demonstrated 37

38 Connection merging in SRA datapath In In 2 M N R R 2 R 3 A B C D E F G H >> >>3 [ abs/max] K L [ abs/min/+/- ] I J Out (a) Datapath for SRA Bus = [ A, C, D, E, H ] Bus2 = [ B, F, G ] Bus3= [ I, K, M ] Bus4 = [ J, L, N ] (e) Bus assignment A B C D E F G H I J K L M N s 3 s 6 (b) Connectivity usage table s 7 (c) Compatibility graph for input buses 38 (d) Compatibility graph for output buses

39 Connection merging in SRA datapath In In 2 M N R R 2 R 3 A B C D E F G H >> >>3 [ abs/max] K L [ abs/min/+/- ] I J Out Datapath for SRA Bus = [ A, C, D, E, H ] Bus2 = [ B, F, G ] Bus3= [ I, K, M ] Bus4 = [ J, L, N ] Bus assignment R R 2 R 3 Bu Bu [ abs/min] [ abs/max/+/- ] >> >>3 Bus 3 Bu (f) Bus oriented datapath 39

40 Register merging Group register with nonoverlapping accesses Each group assigned to one register file Register grouping reduces number of ports, and therefore number of buses Demonstration with clustering algorithm 4

41 Register merging R = In R 2 = In2 Start R = [ a, t, x, t 7 ] R 2 = [ b, t 2, y, t 3, t 5, t 6 ] R 3 = [ t 4 ] R = R R 2 = R 2 (a) Register assignment R = max (R, R 2 ) R 2 = min (R, R 2 ) s 3 R 2 = R >> 3 R 3 = R 2 >> R R 2 R 3 s 3 s 6 s 7 R R 2 [ / ] R 3 R 2 = R -R 2 (b) Register access table (c) Compatibility graph R 2 = R 3 + R 2 s 6 R = max (R 2, R ) s 7 Done = Out = R ASM Chart 4 (d) Datapath schematic

42 Chaining and multicycling Chaining allows serial execution of two or more operations in each state Chaining reduces number of states and increases performance Multicycling allows one operation to be executed over two or more clock cycles Multicycling reduces size of functional units Chaining and multicycling are used on noncritical paths to improve resource utilization and performance 42

43 SRA datapath with chained units In In 2 a = In b = In 2 R R 2 R 3 Start = Bu Bu t = a t 2 = b [ abs/max] [ abs/min/+/- ] >>3 >> Bus 3 Bu x = max( t, t 2 ) t 3 = max( t, t 2 )>>3 t 4 = min ( t, t 2 )>> s 3 t 5 = x t 3 Out t 6 = t 4 + t 5 (b) Datapath schematic s 6 t 7 = max ( t 6, x ) Done = In 2 Out = t 7 (a) ASM Chart 43

44 SRA datapath with multicycle units a = In b = In 2 In In 2 Start = t = a t 2 = b x = max( t, t 2 ) t 3 = max( t, t 2 )>>3 t 4 = min ( t, t 2 )>> Bu Bu R R 2 R 3 [ abs/max] [ abs/+/- ] min s 3 t 5 = x t 3 Bus 3 >>3 >> Bu t 6 = t 4 + t 5 t 7 = max ( t 6, x ) Out (b) Datapath schematic s 6 Done = In 2 Out = t 7 (a) ASM Chart 44

45 Pipelining Pipelining improves performance at a very small additional cost Pipelining divides resources into stages and uses all stage concurrently for different data ( assembly line principle) Pipelining principles works on several levels: (a) Units pipelining (b) Control pipelining (c) Datapath pipelining 45

46 Pipelined arithmetic unit c 2 c c latches Adder sign bit 46

47 SRA datapath with single AU a = In b = In 2 Start = t = a t 2 = b x = max( t, t 2 ) t 3 = max( t, t 2 )>>3 [t 4 ] = min ( t, t 2 )>> s 3 t 5 = x t 3 t 4 = [min ( t, t 2 )>>] s 6 t 6 = t 4 + t 5 t 7 = max ( t 6, x ) Done = In 2 Out = t 7 (b) Datapath schematic (a) ASM Chart 47

48 Datapath with pipelined functional unit In In 2 Bu Bu R R 2 R 3 2-stage AU Bus 3 Bu >>3 >> Out (a) Datapath with pipelined AU Read R t 7 t 6 a t t x x 2 Read R 2 b t 2 t 2 t 3 t 5 Read R 3 AU stage a b max min - + max AU stage 2 a b max min - + max t 7 t 6 shifters >>3 >> Write R a t x Write R 2 b t 2 t 3 t 5 Write R 3 Outport s 3 s 6 t 4 s 7 (b) Timing diagram 48 s 8 t 4 s 9 t 7

49 Datapath pipelining In In 2 a = In b = In 2 Bu R R 2 Bu AU t = a Bus 3 >>3 >> Bu t 2 = b s 3 t 4 = min ( t, t 2 ) >> x = max( t, t 2 ) t 3 = max ( t, t 2 )>>3 R 3 R 4 R 5 Bu Bus 6 AU 2 Bus 7 s 6 t 5 = x t 3 Out (b) Pipelined datapath t 6 = t 4 + t 5 s 7 t 7 = max ( t 6, x ) s 8 Done = Out = t 7 (a) ASM Chart R = [ a, t ] R 3 = [ t 3, t 5, t 6, t 7 ] R 2 = [ b, t 2 ] R 4 = [ x ] AU = [ abs/min/max ] R 5 = [ t 4 ] AU2 = [ +/-/max ] (c) Register and functional unit assignment 49

50 Datapath pipelining In In 2 R R 2 Bu Bu AU nth pair (n+)th pair Bus 3 >>3 >> Bu Read R a s 3 t t s 6 s 7 s 8 s 9 Read R2 b t 2 t 2 R 3 R 4 R 5 AU stage a b min max Out Bu Bus 6 AU 2 Bus 7 (b) Pipelined datapath Shifters Write R Write R2 Read R3 Read R4 Read R5 a b t t 2 >> >>3 t 3 x t 5 t 4 t 6 x t 7 AU stage 2 Write R3 t 3 - t 5 + t 6 max t 7 Write R4 x Write R5 t 4 nth pair 5 (d) Timing diagram

51 Timing diagram for datapath pipeline with pipelined units Read R Read R2 AU stage AU stage 2 Shifters Write R Write R2 Read R3 Read R4 Read R5 AU2 stage AU2 stage 2 Write R3 Write R4 Write R5 Out a b a a b b a t s 3 t t 2 b t 2 s 6 t t 2 min max min max >> >>3 t 4 t 3 x s 7 t 3 x - s 8 - t 5 s 9 t 5 t t 6 2 t 6 x max max t 7 t 4 3 t 7 t 3 x t 7 5

52 Pipelined FSMD implementation / (a) Standard FSMD implementation / (b) FSMD implementation with control and datapath pipelining 52

53 ASM charts for pipelined FSMDs / (b) FSMD implementation with control and datapath pipelining (a) ASM chart (b) ASM chart (c) ASM chart for for control control pipeline with pipeline with status register and status register 53 control registers (d) ASM chart for control and datapath pipeline

54 Scheduling RT description such as ASM chart specifies data operations in each state Flowcharts or programming languages do not have states, but only specify order in which operations are executed. Scheduling transforms flowcharts or programs with RT descriptions Two types of scheduling (a) resource constrained (resource given, minimize time) (b) time constrained (time given, minimize resources) 54

55 Control/dataflow graph for SRA a=in b=in 2 In In 2 a b a>b Start t = a t 2 = b x=max (t, t 2 ) y=min(t, t 2 ) t 3 =x>>3 t 4 =y>> t 5 =x-t 3 t 6 =t 4 +t 5 t 7 = max(t 6,x) Done= Out=t 7 a b a b min max >> >>3 - + max Out Done (a) Flowchart 55 (b) Control/Data flow graph

56 Basic schedules (a) ASAP schedule 56 (a) ALAP schedule

57 List scheduling algorithm 57

58 Resource-constrained constrained scheduling Perfrom ASAP Perfrom ALAP Determine mobilities Create ready list Sort ready list by mobilities Schedule ops from ready list Delete scheduled ops from ready list Add new ops to ready list Increment state index no All ops scheduled? yes (a) ASAP (b) ALAP (c) Ready list with mobilities (d) RC schedule 58

59 Time-constrained scheduling Perfrom ASAP Perfrom ALAP Determine mobilities ranges Create probability distribution graphs no All ops scheduled? yes All ops scheduled? yes Schedule ops from ready list Schedule ops from ready list 59

60 TC schedule for SRA algorithm a b a min max a b b s 3 >> >>3 max max - min >>3 min >>3 + >> - >> - s 6 max + + s 7 max max Out s 8 Out (a) ASAP (b) ALAP (c) TC schedule 6

61 Probability distribution graph before, during and after TC scheduling (a) Initial probability distribution graph (b) Distribution graph after max, + and were scheduled (c) Distribution graph after max, + and,>>3 and >> were scheduled 6 (c) Distribution graph for final scheduled

62 We introduced RT design: FSMD model RT specification with Chapter summary Procedure for synthesis from RT specification Design Optimization through Design Pipelining Static-action tables ASM charts Register sharing Unit chaining Functional unit sharing Multiclocking Bus sharing Unit pipelining Control pipelining Datapath pipelining Scheduling of flowcharts 62

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