UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
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1 UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002 Date: Wednesday 17 May 2017 Time: INSTRUCTIONS TO CANDIDATES: There are five (5) questions. Answer any four (4) questions. All questions carry equal marks. Marks for parts of questions are shown in brackets. Time: 2 hours CANDIDATES REQUIRE: Answer book
2 Page 2 of 6 Q1. (a) In the circuit shown below (Figure 1), the output Y of the flip-flop is connected to its input via an inverter. Draw the output waveform assuming that the output Y is initially LOW and the CLK is a square wave. Figure 1: A flip-flop circuit (b) A group of digital logic designers working for National Instruments could not agree on whether to use NAND gates or NOR gates to build a set-reset latch. The compromise design is shown in Figure 2. Figure 2: A digital logic circuit (i) Fill in the function table (Table 1) for Q and Q in this sequential circuit and reproduce this table in your answer sheet. Question 1 continued over the page
3 Page 3 of 6 Question 1 continued over the page X Y Q /Q Table 1: Sequential Circuit (ii) From the completed function table, explain what is wrong with this Latch. How can the design be corrected? (c) For a Verilog code, the following number has been defined: 8`d255. How many bits does the number have and what will the representation for the same number in binary format? Q2. A sequential circuit with D Flip-Flops A and B, one input X, and one output Z is specified by the following input equations: D A = X A + XB D B = B X Z = AB (a) Draw the circuit diagram represented by the above equations. Question 2 continued over the page
4 Page 4 of 6 Question 2 continued (b) (c) For the circuit defined by above equations, derive the state table. For the circuit defined by above equations, derive the state diagram. Q3. (a) For the Mealy FSM shown below (Figure 3), draw the equivalent Moore machine Figure 3: A Mealy FSM (15 marks) (b) Considering, for the Mealy Machine shown above, if the input sequence is 011, then the corresponding output sequence, Q1 0/Z1 Q2 1/Z1 Q3 1/Z2 Q3, would be Z1Z1Z2. (i) What would be output sequence if the input is fixed to a constant 1 for all cycles? Question 3 continued over turn the page
5 Page 5 of 6 Question 3 continued (ii) What would be output sequence if the input is fixed to a constant 0 for all cycles? Q4. A 3-bit counter is required that follows the sequence: 000, 001, 011, 100, 101, 000, 001, 011, 100, 101. Design the logic circuit for a Mealy Finite State Machine (FSM) to follow this sequence using D-type Flip Flops and as few gates as possible by utilizing the don t-care conditions arising from the not-used states. 25 marks Q5. (a) Draw and describe the construction of a single static RAM memory cell incorporating the SR -latch and associated gates. (b) Considering the binary weighted D/A convertor shown below (Figure 3), determine the voltage at Vout if the binary equivalent of 1010 is input on switches D3 to D0? Question 5 continued over the page
6 Page 6 of 6 Question 5 continued Figure 3: A binary weighted D/A convertor (c) Given below is a 3-stage shift register (Figure 4) consisting of 3 Flip-flops. Provide the Verilog code for the circuit below using appropriate procedural statements. Figure 4: A 3-stage shift register -----End of questions-----
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