University of Guelph School of Engineering ENG 2410 Digital Design Fall There are 7 questions, answer all questions.

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1 Final Examination Instructor: Shawki M. Areibi Co-examiner: Medhat Moussa. Location: UOG Date: Wednesday, December 5th, 2007 Time: 8:30-10:30 AM Duration: 2 hours. Type: R Closed Book. Instructions: University of Guelph School of Engineering ENG 2410 Digital Design Fall There are 7 questions, answer all questions. 2. Characteristic Tables and Excitation Tables are appended to the examination paper. 3. The total number of pages in the examination booklet is 16 excluding the page for the characteristic/excitation tables. 4. Any combinational logic design question implies deriving the truth table, simplification, and drawing the logic diagram (unless stated otherwise). 5. Any sequential logic design question implies deriving the state diagram, state table, and the logic diagram (unless stated otherwise). Name Id number 1 of 17

2 For use of examiner mark out of Question 1 3 Question 2 6 Question 3 6 Question 4 7 Question 5 8 Question 6 7 Question 7 8 Total 45 2 of 17

3 Question 1. Definitions [3 marks ] Part A. Technical Terms [3 marks] Explain the following technical terms briefly: i. VHDL. ii. RTL. iii. Behavioral Description in VHDL. iv. Transparency of latches. v. ASM. vi. Mealy Machine. 3 of 17

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5 Question 2. Combinational Logic Design [6 marks ] Part A. Half Adder [6 marks] i. Design a half-adder that has two inputs A 0 and B 0 and two outputs Sum (S) and Carry (C). Start with the truth table and draw the circuit (Do not simplify the design!) ii. Write the VHDL equivalent (entity and architecture) of the half-adder that you designed using a data flow representation. iii. What is the importance of using hierarchy to design any digital system? 5 of 17

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7 Question 3. Combinational Logic [6 marks ] Part A. Minterms and Maxterms [6 marks] Given the following Boolean Function: F(A, B, C) = M(0, 3, 5) i. Draw a truth table of the function F. ii. What are the minterms of the function? iii. What are the maxterms of the function? iv. Derive a simplified expresion for F using K-Maps. v. Draw the logic diagram corresponding to the simplified boolean experssion derived. vi. Use a decoder to implement the function F. 7 of 17

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9 Question 4. Sequential Logic [7 marks ] Part A. Design [7 marks] Design a sequential circuit with D flip-flops and single input X. If X = 0, the circuit remains in the same state. When X = 1, the circuit goes through the state transition from 00 to 11 to 10 to 01, back to 00, and then repeats. i. Draw the state diagram that represents the states and transitions. ii. Obtain the state table. iii. Derive the input equations of the flip flops in simplified form. iv. Draw the logic diagram of the circuit. 9 of 17

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11 Question 5. Data Path Design [8 marks ] Part A. Arithmetic Unit [8 marks] Design a 4-bit arithmetic circuit with two inputs A and B using the concept of hierarchy. Use a Full Adder (with two inputs X and Y and a carry in C in ) and Multiplexors (with two control lines) to implement a single stage of Table 1. The circuit has two selection variables S 1 and S 0 that generates the following arithmetic operations: S 1 S 0 C in = 0 C in = F = A + B (add) F = A + B F = A(Transfer) F = A + 1 (increment) 1 0 F = B (complement) F = B + 1 (negate) 1 1 F = A + B F = A + B + 1 (subtract) Table 1: Selection Table Draw the logic diagram for a single bit stage. Use hierarchy to extend the design to a 4-bit circuit. 11 of 17

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13 Question 6. Memory Design [7 marks ] Part A. Memory Expansion [7 marks] A 64K 8 RAM chip is shown in Figure 1. 64K x 8 RAM Input Data 8 Address A0 A15 Chip Select Read/Write DATA ADRS CS R/W 8 Output Data Figure 1: Symbol for a 64K x 8 RAM chip i. Answer the following questions related to memory technology: Give two reasons why DRAM is slower than SRAM. What does the inverted triangle in Figure 1 indicate? ii. How many 64K 8 RAM chips are needed to provide a memory capacity of 128K x 24bit? How many address lines are required? iii. Construct the block diagram of 128K x 24bit using the 64K x 8 RAM and a decoder. Show the address lines, data lines, R/W in detail. 13 of 17

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15 Question 7. ASM & Control [8 marks ] Part A. Algorithmic State Machines [8 marks] Figure 2 shows a state diagram with four states /1 0 01/ /0 0 11/0 1 0 Figure 2: State Diagram i. What type of sequential machine does the state diagram represent? ii. Draw the corresponding Algorithmic State Machine (ASM). iii. Implement the design of the control unit using a sequence register and decoder. Do not simplify the input equations of the D Flip Flops. (Hint: Derive the state table and input equations to the D Flip-Flops). iv. If you were to use VHDL to design a control unit what type of architecture model would you use (dataflow, structural or behavioral)? Why? 15 of 17

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17 Continue Solutions.. Q7 [45 marks grand total] 17 of 17

COMBINATIONAL LOGIC FUNCTIONS

COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present