CSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid

Size: px
Start display at page:

Download "CSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid"

Transcription

1 CSE140: Components and Design Techniques for Digital Systems Midterm Information Instructor: Mohsen Imani

2 Midterm Topics In general: everything that was covered in homework 1 and 2 and related lectures, such as: Transistors Boolean algebra Basic gates Logic functions and truth tables Canonical forms (SOP and POS) Two-level logic minimization Kmaps Multiplexers (behavior and how to implement logic functions with them) Decoders (behavior and how to implement logic functions with them) Midterm is in PCYNH 122 on Thr 08/24 2

3 Midterm Logistics Do not start the exam until you are told. Write your name and PID at the top of every page. Write the names of people on your left and right on the first page. Turn off and put away all your electronics. This is a closedbook, closednotes exam. If you have a question, raise your hand and an exam proctor will come to you. You have 60 minutes to finish the exam. When the time is finished, you must stop writing. Report the solutions in the spaces provided. Only the front pages will be graded. We will not consider anything written on the back of the pages. Any student violating UCSD's Academic Dishonesty or UCSD's Student Conduct policies will earn an 'F' in the CSE140 course and will be reported to their college Dean for administrative processing. When returning your exam, also show your student ID. Write your answers in the space provided. To get the most partial credit, clearly show all the steps of your work. Full credit may not be given for correct answers with no work shown. 3

4 CSE140: Components and Design Techniques for Digital Systems Sequential Circuit Introduction Latches and Flip-Flops

5 SR Latch Analysis S = 1, R = 0: then = 1 and = 0 R 0 0 N1 1 S 0 1 N2 0 S = 0, R = 1: then = 1 and = 0 R 1 1 N1 0 S 0 0 N2 1

6 SR Latch Analysis S = 0, R = 0: prev = 0 prev = 1 then = prev Memory! R 0 N1 0 R 0 N1 S 0 N2 S 0 N2 S = 1, R = 1: then = 0, = 0 Invalid State NOT R S N1 N2 0 0

7 SR Latch Symbol SR stands for Set/Reset Latch Stores one bit of state () Control what value is being stored with S, R inputs Set: Make the output 1 (S = 1, R = 0, = 1) Reset: Make the output 0 (S = 0, R = 1, = 0) Hold: Keep data stored (S = 0, R = 0, = previous ) SR Latch Symbol R S

8 Add input C Avoiding S=R=1 Part 1: Level-Sensitive SR Latch Change C to 1 only after S and R are stable C is usually a clock (CLK) S Level-sensitive SR latch S1 C R R1

9 D Latch Truth Table CLK D R R D S S CLK D 0 X D X 1 0 S R 0 0 prev prev 1 0

10 D Latch Summary Two inputs: CLK, D CLK: controls when the output changes D (the data input): controls what the output changes to Function When CLK = 1, D passes through to (transparent) When CLK = 0, holds its previous value (opaque) (Mostly) avoids invalid case = D Latch Symbol D CLK

11 D Latch Truth Table CLK D R R D S S CLK D 0 X D X 1 0 S R 0 0 prev prev 1 0

12 D-Latch 12

13 The D flip-flop 13

14 Latches versus flip-flops 14

15 The master-slave D 15

16 Bit Storage Overview SR latch S (set) R (reset) Level-sensitive SR latch S S1 C R R1 D C S R D latch D Clk D latch Dmm Cm master D flip-flop D latch Ds s Cs s servant S=1 sets to 1, R=1 resets to 0. Problem: SR=11 yield undefined. S and R only have effect when C=1. We can design outside circuit so SR=11 never happens when C=1. Problem: avoiding SR=11 can be a burden. SR can t be 11 if D is stable before and while C=1, and will be 11 for only a brief glitch even if D changes while C=1. Problem: C=1 too long propagates new values through too many latches: too short may not enable a store. Only loads D value present at rising clock edge, so values can t propagate to other flipflops during same clock cycle. Tradeoff: uses more gates internally than D latch, and requires more external gates than SR but gate count is less of an issue today. 16

17 Rising vs. Falling Edge D Flip-Flop The triangle means clock input, edge triggered D Symbol for rising-edge triggered D flip-flop rising edges Clk D Symbol for falling-edge triggered D flip-flop Clk falling edges Internal design: Just invert servant clock rather than master 17

18 Enabled D-FFs Inputs: CLK, D, EN The enable input (EN) controls when new data (D) is stored Function EN = 1: D passes through to on the clock edge EN = 0: the flip-flop retains its previous state EN Internal Circuit CLK Symbol D 0 1 D D EN

19 Additional D-FF Features Reset (set state to 0) R synchronous: Dnew = R' Dold (when next clock edge arrives) asynchronous: doesn't wait for clock Preset or set (set state to 1) S (or sometimes P) synchronous: Dnew = Dold + S (when next clock edge arrives) asynchronous: doesn't wait for clock Both reset and preset Dnew = R' Dold + S (set-dominant) Dnew = R' Dold + R'S (reset-dominant) Selective input capability (input enable or load) LD or EN multiplexor at input: Dnew = LD' + LD Dold load may or may not override reset/set (usually R/S have priority) 19

20 Registers and Counters 20

21 Building blocks with FFs: Basic Register Register: a sequential component that can store multiple bits A basic register can be built simply by using multiple D-FFs OUT1 OUT2 OUT3 OUT4 CLK D D D D IN1 IN2 IN3 IN4 I3 I2 I1 I0 reg(4)

22 Shift register Holds & shifts samples of input OUT1 OUT2 OUT3 OUT4 IN D D D D CLK 22

23 Pattern Recognizer Combinational function of input samples OUT OUT1 OUT2 OUT3 OUT4 IN D D D D CLK 23

24 Counters Sequences through a fixed set of patterns Note: definition is general For example, the one in the figure is a type of counter called Linear Feedback Shift Register (LFSR) OUT1 OUT2 OUT3 OUT4 IN D D D D CLK 24

25 General Counters Default operation: count up A-D counter output A-D parallel load data LOAD enables data load RCO ripple carry out CLR clears data EN counter enable "1" "0" "1" "1" "0" "0" EN RCO D D C C B B A A LOAD CLK CLR Similar signals can also be used for registers You can generalize these ideas to build multifunction registers/shifters/counters with a variety of control signals (load, clear, enable, etc.) "1" "0" "0" "0" "0" EN RCO D D C C B B A A LOAD CLK CLR 25

26 Finite State Machines 26

27 Circuit Specifications Combinational Logic Truth tables, Boolean equations, logic diagrams (no feedback) Sequential Networks: State Diagram (Memory) State and Excitation Tables Characteristic Expression Logic Diagram (FFs and feedback loops) Y A B C D Combinational X CLK CLK RTL: Register-Transfer Level Description CLK 27

28 Finite State Machines: Two Bit Counter Example Symbol/ Circuit 2 bit Counter Current state S 0 S 1 S 1 S 2 S 2 S 3 S 3 S 0 Next State For example: S0: Breakfast S1: Lunch S2: Dinner S3: Sleep For example: Count up to 11 S 0 S 3 S 1 1 (t) 0 (t) 1 (t+1) 0 (t+1) S State Diagram State Table

29 1 (t) 0 (t) 1 (t+1) 0 (t+1)

30 Which is the most likely circuit realization of the two bit counter? State Table 1 (t) 0 (t) 1 (t+1) 0 (t+1) A. Combinational circuit Circuit with no flip flops B. C. 0 (t) Combinational circuit 1 (t) D D CLK 0 (t) 1 (t) Combinational circuit D CLK Circuit with 2 flip flops Circuit with one flip flop

31 Two Bit Counter Circuit State Table 1 (t) 0 (t) 1 (t+1) 0 (t+1) D 0 (t) 0 (t) D 1 (t) 1 (t) D D CLK We store the current state using D-flip flops so that: Inputs to the combinational circuit don t change while the next output is computed The transition to the next state only occurs at the rising edge of the clock D 0 (t) = 0 (t) D 1 (t) = 0 (t) 1 (t) + 0 (t) 1 (t) Implementation of 2-bit counter

32 FSM Definition FSM consists of Set of states Set of inputs, set of outputs Initial state I a b A B Set of transitions Only one can be true at a time FSM representations: State diagram State table 32

33 FSM Controller Design Process with a Three Bit Counter Example 1. State Diagram 2. State Table State Assignments Excitation Table (present state, inputs; next state, outputs) 5. Circuit State Table with Assigned State Patterns C3 C2 C1 N3 N2 N CLK "1" bit up-counter FSM 110 Circuit D D D 100 OUT1 OUT2 OUT3 33

34 Mealy and Moore Machines x(t) Mealy Machine Moore Machine C1 C2 y(t) x(t) C1 C2 y(t) CLK S(t) y i (t) = f i (X(t), S(t)) Output is the function of the present state as well as the input! CLK y i (t) = f i (S(t)) S(t) Output is the only function of current state ONLY!

35 What s this state machine? A. Mealy State machine B. Moore state machine C. Can be both D. I don t know 35

36 Life on Mars? Mars rover has a binary input x. When it receives the input sequence x(t-2, t) = 001 from its life detection sensors, it means that the it has detected life on Mars and the output y(t) = 1, otherwise y(t) = 0 (no life on Mars). This pattern recognizer should have A.One state because it has one output B.One state because it has one input C.Two states because the input can be 0 or 1 D.More than two states because. E.None of the above 36

37 Mars Life Recognizer FSM Which of the following diagrams is a correct Mealy solution for the 001 pattern recognizer on the Mars rover? 1/1 A. 1/0 S0 0/0 S1 0/0 S2 0/0 1/0 B. 1/0 0/0 S0 0/0 S1 1/1 S2 1/0 C. Both A and B are correct 0/0 D. None of the above 37

38 State Diagram => State Table with State Assignment 1/1 x(t) 1/0 S0 0/0 1/0 S1 0/0 S2 0/0 C1 C2 CLK S(t) Mealy Machine y(t) S(t)\x 0 1 S0 S1,0 S0,0 S1 S2,0 S0,0 S2 S2,0 S0,1 State Assignment S0: 00 S1: 01 S2: 10 S(t)\x ,0 00, ,0 00, ,0 00,1 1 (t+1) 0 (t+1), y 38

39 State Diagram => State Table => Excitation Table => Circuit 1 (t) 0 (t)\x ,0 00, ,0 00, ,0 00,1 x(t) C1 C2 CLK S(t) Mealy Machine y(t) id 1 0 x D 1 D 0 y X X X X X X 39

40 State Diagram => State Table => Excitation Table => Circuit id 1 0 x D 1 D 0 y X X X X X X D1(t): x(t) X X 0 D1(t) = x 0 + x 1 D0 (t)= 1 0 x y= 1 x 1 40

41 State Diagram => State Table => Excitation Table => Circuit 1 0 x x 0 D0 D1 D D 0 1 y 1 x x(t) D1(t) = x 0 + x 1 D0 (t)= 1 0 x y= 1 x C1 C2 CLK S(t) Mealy Machine y(t) 41

42 Moore Mars Life Recognizer: Summary 1 S0 0 0 S S S3 1 1 S(t)\x 0 1 S0 S1,0 S0,0 S1 S2,0 S0,0 S2 S2,0 S3,0 S3 S1,1 S0,1 1 0 \x ,0 00, ,0 00, ,0 11, ,1 00,1 1 (t+1) 0 (t+1), y 0 ID 1 0 x D 1 D 0 y

43 Mars Life Recognizer: Summary id 1 0 x D 1 D 0 y D1(t): D0(t): y(t): x(t) x(t) x(t) Sources: TSR, Katz, 1 Boriello & Vahid

44 44

45 CSE140: Components and Design Techniques for Digital Systems Review questions 45

46 Example 1: Multiplexers Derive each intermediate signal as a function of a, b, c and d b 00 4:1 MUX a c 1 w s d out c z 11 s1 s0 b d

47 Example 2: Multiplexers Implement the following function using a 4:1 MUX F(a,b,c) = a b c + a(bc +bc )

48 Example 3: Decoders Derive each intermediate signal as a function of a, b, and c 3:8 Decoder a c a b w A0 A1 A2 A0 A1 A s z out

49 Example 4: Decoders Implement the following function using a 3:8 Decoder F(a,b,c) = abc + a(b c +bc ) 49

50 Multiple-Output Circuits Many circuits have more than one output Can give each a separate circuit, or can share gates Ex: F = ab + c, G = ab + bc Option 1: Separate circuits Option 2: Shared gates 50

51 Primes and Essential Primes Given the following function: F(A,B,C,D) = m(0,2,6,7,8,10) + d(1,11,12,15) a) List all prime implicants b) Identify the essential prime implicants c) Give min cover in SoP (Sum-of-Product) form A D C B 51

52 F(A,B,C,D)= Π M(2, 3, 6, 8, 9, 12, 13, 14) K-maps and Muxes A D C B 52

53 Mux/Demux 53

54 Design problem distance between numbers Design a circuit that gives the absolute distance between the two numbers (e.g. x=3 y=1 d=2) 54

55 NAND gates implementation 55

56 Decoder Implement F(A,B, C) = A C + AC with a minimum size circuit. You may use a 2:4 decoder and minimum number of other gates. 56

ALU, Latches and Flip-Flops

ALU, Latches and Flip-Flops CSE14: Components and Design Techniques for Digital Systems ALU, Latches and Flip-Flops Tajana Simunic Rosing Where we are. Last time: ALUs Plan for today: ALU example, latches and flip flops Exam #1 grades

More information

CSE140: Digital Logic Design Registers and Counters

CSE140: Digital Logic Design Registers and Counters CSE14: Digital Logic Design Registers and Counters Prof. Tajana Simunic Rosing 38 Where we are now. What we covered last time: ALUs, SR Latch Latches and FlipFlops (FFs) Registers What we ll do next FSMs

More information

Lecture 7: Sequential Networks

Lecture 7: Sequential Networks CSE 140: Components and Design Techniques for Digital Systems Lecture 7: Sequential Networks CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1 Part II: Sequential

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance

More information

CSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015

CSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015 CSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015 Name of the person on your left : Name of the person on your right: 1. 20 points 2. 20 points 3. 20 points 4. 15 points 5. 15 points 6. 10

More information

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering SEQUENTIAL CIRCUITS: LATCHES Overview Circuits require memory to store intermediate

More information

CPE100: Digital Logic Design I

CPE100: Digital Logic Design I Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm02 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Nov. 16 th In normal lecture (13:00-14:15)

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing

More information

Synchronous Sequential Logic

Synchronous Sequential Logic 1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in

More information

Lecture 8: Sequential Networks and Finite State Machines

Lecture 8: Sequential Networks and Finite State Machines Lecture 8: Sequential Networks and Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Spring 2014 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University

More information

Sequential vs. Combinational

Sequential vs. Combinational Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current

More information

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final

More information

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3 Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible

More information

Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd..

Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd.. Indian Institute of Technology Jodhpur, Year 2017-2018 Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd.. Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in

More information

CSE 140 Midterm 2 Tajana Simunic Rosing. Spring 2008

CSE 140 Midterm 2 Tajana Simunic Rosing. Spring 2008 CSE 14 Midterm 2 Tajana Simunic Rosing Spring 28 Do not start the exam until you are told to. Turn off any cell phones or pagers. Write your name and PID at the top of every page. Do not separate the pages.

More information

vidyarthiplus.com vidyarthiplus.com vidyarthiplus.com ANNA UNIVERSITY- COMBATORE B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009. ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER DIGITAL LOGIC CIRCUITS PART-A

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

More information

Review for Final Exam

Review for Final Exam CSE140: Components and Design Techniques for Digital Systems Review for Final Exam Mohsen Imani CAPE Please submit your evaluations!!!! RTL design Use the RTL design process to design a system that has

More information

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

More information

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes

More information

Lecture 7: Logic design. Combinational logic circuits

Lecture 7: Logic design. Combinational logic circuits /24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic

More information

LOGIC CIRCUITS. Basic Experiment and Design of Electronics

LOGIC CIRCUITS. Basic Experiment and Design of Electronics Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output

More information

Fundamentals of Digital Design

Fundamentals of Digital Design Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric

More information

CPE100: Digital Logic Design I

CPE100: Digital Logic Design I Chapter 3 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe1/ CPE1: Digital Logic Design I Section 14: Dr. Morris Sequential Logic Design Chapter 3 Chapter

More information

Generalized FSM model: Moore and Mealy

Generalized FSM model: Moore and Mealy Lecture 18 Logistics HW7 is due on Monday (and topic included in midterm 2) Midterm 2 on Wednesday in lecture slot cover materials up to today s lecture Review session Tuesday 4:15pm in EEB125 Last lecture

More information

Computers also need devices capable of Storing data and information Performing mathematical operations on such data

Computers also need devices capable of Storing data and information Performing mathematical operations on such data Sequential Machines Introduction Logic devices examined so far Combinational Output function of input only Output valid as long as input true Change input change output Computers also need devices capable

More information

Timing Constraints in Sequential Designs. 63 Sources: TSR, Katz, Boriello & Vahid

Timing Constraints in Sequential Designs. 63 Sources: TSR, Katz, Boriello & Vahid Timing Constraints in Sequential esigns 63 Sources: TSR, Katz, Boriello & Vahid Where we are now. What we covered last time: FSMs What we ll do next: Timing constraints Upcoming deadlines: ZyBook today:

More information

S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques

S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12] Q.1(a) (i) Derive AND gate and OR gate

More information

EE 209 Logic Cumulative Exam Name:

EE 209 Logic Cumulative Exam Name: EE 209 Logic Cumulative Exam Name: 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines: true / false b.) An 8-to-1 mux and no other logi can be

More information

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE Estd-1984 KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE 641 006 QUESTION BANK UNIT I PART A ISO 9001:2000 Certified 1. Convert (100001110.010) 2 to a decimal number. 2. Find the canonical SOP for the function

More information

Adders allow computers to add numbers 2-bit ripple-carry adder

Adders allow computers to add numbers 2-bit ripple-carry adder Lecture 12 Logistics HW was due yesterday HW5 was out yesterday (due next Wednesday) Feedback: thank you! Things to work on: ig picture, ook chapters, Exam comments Last lecture dders Today Clarification

More information

Faculty of Engineering. FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY

Faculty of Engineering. FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY 1 McGill University Faculty of Engineering DIGITAL SYSTEM DESIGN ECSE-323 FINAL EXAMINATION FALL 2008 (December2008) ANSWER KEY STUDENT NAME McGILL I.D. NUMBER Examiner: Prof. J. Clark Signature: Associate

More information

Topic 8: Sequential Circuits

Topic 8: Sequential Circuits Topic 8: Sequential Circuits Readings : Patterson & Hennesy, Appendix B.4 - B.6 Goals Basic Principles behind Memory Elements Clocks Applications of sequential circuits Introduction to the concept of the

More information

UNIVERSITY OF WISCONSIN MADISON

UNIVERSITY OF WISCONSIN MADISON CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON Prof. Gurindar Sohi TAs: Minsub Shin, Lisa Ossian, Sujith Surendran Midterm Examination 2 In Class (50 minutes) Friday,

More information

Vidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution

Vidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should

More information

Introduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010

Introduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010 EE 224: INTROUCTION TO IGITAL CIRCUITS & COMPUTER ESIGN Lecture 6: Sequential Logic 3 Registers & Counters 05/10/2010 Avinash Kodi, kodi@ohio.edu Introduction 2 A Flip-Flop stores one bit of information

More information

Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2017/2018 Dept. of Computer Engineering Course Title: Logic Circuits Date: 29/01/2018

More information

Chapter 3. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 3 <1>

Chapter 3. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 3 <1> Chapter 3 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 3 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous Logic Design Finite

More information

CPE100: Digital Logic Design I

CPE100: Digital Logic Design I Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Final Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Tuesday Dec 12 th 13:00-15:00 (1-3pm) 2 hour

More information

Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec 09 Counters Outline.

Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec 09 Counters Outline. Review: esigning with FSM EECS 150 - Components and esign Techniques for igital Systems Lec 09 Counters 9-28-0 avid Culler Electrical Engineering and Computer Sciences University of California, Berkeley

More information

Sequential Logic Circuits

Sequential Logic Circuits Chapter 4 Sequential Logic Circuits 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of a sequential circuit,

More information

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering Sp 6 Reg. No. Question Paper Code : 27156 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015. Second Semester Computer Science and Engineering CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common

More information

Chapter 4. Sequential Logic Circuits

Chapter 4. Sequential Logic Circuits Chapter 4 Sequential Logic Circuits 1 2 Chapter 4 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of

More information

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017 UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002

More information

Digital Design. Sequential Logic

Digital Design. Sequential Logic Principles Of igital esign Chapter 6 Sequential Logic Chapter preview Boolean algebra 3 Logic gates and flip-flops 3 Finite-state machine 6 Logic design techniques 4 Sequential design techniques 6 Binary

More information

ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES

ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES EC 216(R-15) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN

More information

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D. Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor

More information

Sample Test Paper - I

Sample Test Paper - I Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:

More information

Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec09 Counters Outline.

Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec09 Counters Outline. Review: Designing with FSM EECS 150 - Components and Design Techniques for Digital Systems Lec09 Counters 9-28-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

More information

Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs

Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR

More information

Last lecture Counter design Finite state machine started vending machine example. Today Continue on the vending machine example Moore/Mealy machines

Last lecture Counter design Finite state machine started vending machine example. Today Continue on the vending machine example Moore/Mealy machines Lecture 2 Logistics HW6 due Wednesday Lab 7 this week (Tuesday exception) Midterm 2 Friday (covers material up to simple FSM (today)) Review on Thursday Yoky office hour on Friday moved to Thursday 2-:2pm

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of Computer Systems Review for the Midterm Stephen A. Edwards Columbia University Spring 22 The Midterm 75 minutes 4 5 problems Closed book Simple calculators are OK, but unnecessary One double-sided

More information

CSE 140: Components and Design Techniques for Digital Systems. Lecture 9: Sequential Networks: Implementation

CSE 140: Components and Design Techniques for Digital Systems. Lecture 9: Sequential Networks: Implementation CSE 4: Components and Design Techniques for Digital Systems Lecture 9: Sequential Networks: Implementation CK Cheng Dept. of Computer Science and Engineering University of California, San Diego Implementation

More information

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: J. Rose and

More information

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI DEPARTMENT: ECE MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 QUESTION BANK SUBJECT NAME: DIGITAL ELECTRONICS UNIT : Design of Sequential Circuits PART A ( Marks). Draw the logic diagram 4: Multiplexer.(AUC

More information

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html

More information

Lecture 3 Review on Digital Logic (Part 2)

Lecture 3 Review on Digital Logic (Part 2) Lecture 3 Review on Digital Logic (Part 2) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ircuit Optimization Simplest implementation ost criterion literal

More information

Sequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science

Sequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science Sequential Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design Sequential Logic Combinational circuits with memory

More information

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO UN IVERSIT Y O F CA LIFO RNI A AT BERKELEY BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO SAN TA BARBA RA S AN TA CRUZ De p a r tm en t of Ele ctr i ca l En gin e e rin g a

More information

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1 Ch 7. Finite State Machines VII - Finite State Machines Contemporary Logic esign 1 Finite State Machines Sequential circuits primitive sequential elements combinational logic Models for representing sequential

More information

Lecture 14: State Tables, Diagrams, Latches, and Flip Flop

Lecture 14: State Tables, Diagrams, Latches, and Flip Flop EE210: Switching Systems Lecture 14: State Tables, Diagrams, Latches, and Flip Flop Prof. YingLi Tian Nov. 6, 2017 Department of Electrical Engineering The City College of New York The City University

More information

Memory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1

Memory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1 Memory Elements I CS31 Pascal Van Hentenryck CS031 Lecture 6 Page 1 Memory Elements (I) Combinational devices are good for computing Boolean functions pocket calculator Computers also need to remember

More information

CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh

CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh CS/COE54: Introduction to Computer Architecture Logic Design Review Sangyeun Cho Computer Science Department Logic design? Digital hardware is implemented by way of logic design Digital circuits process

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits - 1 guntzel@inf.ufsc.br

More information

Chapter 7 Sequential Logic

Chapter 7 Sequential Logic Chapter 7 Sequential Logic SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} March 28, 2016 Table of Contents 1 Intro 2 Bistable Circuits 3 FF Characteristics

More information

ECE 341. Lecture # 3

ECE 341. Lecture # 3 ECE 341 Lecture # 3 Instructor: Zeshan Chishti zeshan@ece.pdx.edu October 7, 2013 Portland State University Lecture Topics Counters Finite State Machines Decoders Multiplexers Reference: Appendix A of

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of Computer Systems Review for the Final Stephen A. Edwards Columbia University Summer 25 The Final 2 hours 8 problems Closed book Simple calculators are OK, but unnecessary One double-sided

More information

Preparation of Examination Questions and Exercises: Solutions

Preparation of Examination Questions and Exercises: Solutions Questions Preparation of Examination Questions and Exercises: Solutions. -bit Subtraction: DIF = B - BI B BI BO DIF 2 DIF: B BI 4 6 BI 5 BO: BI BI 4 5 7 3 2 6 7 3 B B B B B DIF = B BI ; B = ( B) BI ( B),

More information

Homework #4. CSE 140 Summer Session Instructor: Mohsen Imani. Only a subset of questions will be graded

Homework #4. CSE 140 Summer Session Instructor: Mohsen Imani. Only a subset of questions will be graded Homework #4 CSE 140 Summer Session 2 2017 Instructor: Mohsen Imani Only a subset of questions will be graded 1) For the circuit shown below, do the following: a. Write a logic equation for the output P

More information

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007 EECS 150 - Components and Design Techniques for Digital Systems FSMs 9/11/2007 Sarah Bird Electrical Engineering and Computer Sciences University of California, Berkeley Slides borrowed from David Culler

More information

Digital Circuits and Systems

Digital Circuits and Systems EE201: Digital Circuits and Systems 4 Sequential Circuits page 1 of 11 EE201: Digital Circuits and Systems Section 4 Sequential Circuits 4.1 Overview of Sequential Circuits: Definition The circuit whose

More information

CSE 140 Midterm 2 - Solutions Prof. Tajana Simunic Rosing Spring 2013

CSE 140 Midterm 2 - Solutions Prof. Tajana Simunic Rosing Spring 2013 CSE 140 Midterm 2 - Solutions Prof. Tajana Simunic Rosing Spring 2013 Do not start the exam until you are told. Write your name and PID at the top of every page. Do not separate the pages. Turn off and

More information

Digital Circuits ECS 371

Digital Circuits ECS 371 Digital Circuits ECS 371 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 18 Office Hours: BKD 3601-7 Monday 9:00-10:30, 1:30-3:30 Tuesday 10:30-11:30 1 Announcement Reading Assignment: Chapter 7: 7-1,

More information

Chapter 7. Sequential Circuits Registers, Counters, RAM

Chapter 7. Sequential Circuits Registers, Counters, RAM Chapter 7. Sequential Circuits Registers, Counters, RAM Register - a group of binary storage elements suitable for holding binary info A group of FFs constitutes a register Commonly used as temporary storage

More information

Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution

Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution . (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)

More information

Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker

Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker Note: + implies OR,. implies AND, ~ implies NOT Question 1: a) (4%) Use transmission gates to design a 3-input OR gate Note: There are

More information

Latches. October 13, 2003 Latches 1

Latches. October 13, 2003 Latches 1 Latches The second part of CS231 focuses on sequential circuits, where we add memory to the hardware that we ve already seen. Our schedule will be very similar to before: We first show how primitive memory

More information

Problem Set 9 Solutions

Problem Set 9 Solutions CSE 26 Digital Computers: Organization and Logical Design - 27 Jon Turner Problem Set 9 Solutions. For each of the sequential circuits shown below, draw in the missing parts of the timing diagrams. You

More information

Schedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date.

Schedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date. Schedule Date Day Class No. Dec Mon 25 Final Review 2 Dec Tue 3 Dec Wed 26 Final Review Title Chapters HW Due date Lab Due date LAB 8 Exam 4 Dec Thu 5 Dec Fri Recitation HW 6 Dec Sat 7 Dec Sun 8 Dec Mon

More information

CSE140: Design of Sequential Logic

CSE140: Design of Sequential Logic CSE4: Design of Sequential Logic Instructor: Mohsen Imani Flip Flops 2 Counter 3 Up counter 4 Up counter 5 FSM with JK-Flip Flop 6 State Table 7 State Table 8 Circuit Minimization 9 Circuit Timing Constraints

More information

Review for B33DV2-Digital Design. Digital Design

Review for B33DV2-Digital Design. Digital Design Review for B33DV2 The Elements of Modern Behaviours Design Representations Blocks Waveforms Gates Truth Tables Boolean Algebra Switches Rapid Prototyping Technologies Circuit Technologies TTL MOS Simulation

More information

State and Finite State Machines

State and Finite State Machines State and Finite State Machines See P&H Appendix C.7. C.8, C.10, C.11 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register

More information

The Design Procedure. Output Equation Determination - Derive output equations from the state table

The Design Procedure. Output Equation Determination - Derive output equations from the state table The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flipflop types

More information

Sequential Synchronous Circuit Analysis

Sequential Synchronous Circuit Analysis Sequential Synchronous Circuit Analysis General Model Current State at time (t) is stored in an array of flip-flops. Next State at time (t+1) is a Boolean function of State and Inputs. Outputs at time

More information

Digital Electronics Sequential Logic

Digital Electronics Sequential Logic /5/27 igital Electronics Sequential Logic r. I. J. Wassell Sequential Logic The logic circuits discussed previously are known as combinational, in that the output depends only on the condition of the latest

More information

S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques

S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12]

More information

ALU A functional unit

ALU A functional unit ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1

More information

Digital Logic Design. Midterm #2

Digital Logic Design. Midterm #2 EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm - igital Logic esign Midterm #2 Problems Points. 5 2. 4 3. 6 Total 5 Was the exam fair? yes no EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm

More information

Synchronous Sequential Circuit Design. Digital Computer Design

Synchronous Sequential Circuit Design. Digital Computer Design Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always

More information

Written exam for IE1204/5 Digital Design with solutions Thursday 29/

Written exam for IE1204/5 Digital Design with solutions Thursday 29/ Written exam for IE4/5 Digital Design with solutions Thursday 9/ 5 9.-. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 8-794487 Exam text does not have to be returned when

More information

Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Final Examination

Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Final Examination Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall 2013-2014 Final Examination CLOSED BOOK Kewal K. Saluja Date:

More information

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)

More information

Logic design? Transistor as a switch. Layered design approach. CS/COE1541: Introduction to Computer Architecture. Logic Design Review.

Logic design? Transistor as a switch. Layered design approach. CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Logic design? CS/COE54: Introduction to Computer rchitecture Digital hardware is implemented by way of logic design Digital circuits process and produce two discrete values: and Example: -bit full adder

More information

Digital Electronics Circuits 2017

Digital Electronics Circuits 2017 JSS SCIENCE AND TECHNOLOGY UNIVERSITY Digital Electronics Circuits (EC37L) Lab in-charge: Dr. Shankraiah Course outcomes: After the completion of laboratory the student will be able to, 1. Simplify, design

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements:., Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University

More information

Chapter 3. Chapter 3 :: Topics. Introduction. Sequential Circuits

Chapter 3. Chapter 3 :: Topics. Introduction. Sequential Circuits Chapter 3 Chapter 3 :: Topics igital esign and Computer Architecture, 2 nd Edition avid Money Harris and Sarah L. Harris Introduction Latches and Flip Flops Synchronous Logic esign Finite State Machines

More information

ECE/Comp Sci 352 Digital Systems Fundamentals. Charles R. Kime Section 2 Fall Logic and Computer Design Fundamentals

ECE/Comp Sci 352 Digital Systems Fundamentals. Charles R. Kime Section 2 Fall Logic and Computer Design Fundamentals University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Charles R. Kime Section 2 Fall 2001 Lecture 5 Registers & Counters Part 2 Charles Kime Counters Counters are sequential circuits

More information

COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University

COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University 1 OEN 312 DIGIAL SYSEMS DESIGN - LEURE NOES oncordia University hapter 6: Registers and ounters NOE: For more examples and detailed description of the material in the lecture notes, please refer to the

More information

EE141- Spring 2007 Digital Integrated Circuits

EE141- Spring 2007 Digital Integrated Circuits EE141- Spring 27 igital Integrated Circuits Lecture 19 Sequential Circuits 1 Administrative Stuff Project Ph. 2 due Tu. 5pm 24 Cory box + email ee141- project@bwrc.eecs.berkeley.edu Hw 8 Posts this Fr.,

More information

Gates and Flip-Flops

Gates and Flip-Flops Gates and Flip-Flops Chris Kervick (11355511) With Evan Sheridan and Tom Power December 2012 On a scale of 1 to 10, how likely is it that this question is using binary?...4? What s a 4? Abstract The operation

More information