CSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid
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1 CSE140: Components and Design Techniques for Digital Systems Midterm Information Instructor: Mohsen Imani
2 Midterm Topics In general: everything that was covered in homework 1 and 2 and related lectures, such as: Transistors Boolean algebra Basic gates Logic functions and truth tables Canonical forms (SOP and POS) Two-level logic minimization Kmaps Multiplexers (behavior and how to implement logic functions with them) Decoders (behavior and how to implement logic functions with them) Midterm is in PCYNH 122 on Thr 08/24 2
3 Midterm Logistics Do not start the exam until you are told. Write your name and PID at the top of every page. Write the names of people on your left and right on the first page. Turn off and put away all your electronics. This is a closedbook, closednotes exam. If you have a question, raise your hand and an exam proctor will come to you. You have 60 minutes to finish the exam. When the time is finished, you must stop writing. Report the solutions in the spaces provided. Only the front pages will be graded. We will not consider anything written on the back of the pages. Any student violating UCSD's Academic Dishonesty or UCSD's Student Conduct policies will earn an 'F' in the CSE140 course and will be reported to their college Dean for administrative processing. When returning your exam, also show your student ID. Write your answers in the space provided. To get the most partial credit, clearly show all the steps of your work. Full credit may not be given for correct answers with no work shown. 3
4 CSE140: Components and Design Techniques for Digital Systems Sequential Circuit Introduction Latches and Flip-Flops
5 SR Latch Analysis S = 1, R = 0: then = 1 and = 0 R 0 0 N1 1 S 0 1 N2 0 S = 0, R = 1: then = 1 and = 0 R 1 1 N1 0 S 0 0 N2 1
6 SR Latch Analysis S = 0, R = 0: prev = 0 prev = 1 then = prev Memory! R 0 N1 0 R 0 N1 S 0 N2 S 0 N2 S = 1, R = 1: then = 0, = 0 Invalid State NOT R S N1 N2 0 0
7 SR Latch Symbol SR stands for Set/Reset Latch Stores one bit of state () Control what value is being stored with S, R inputs Set: Make the output 1 (S = 1, R = 0, = 1) Reset: Make the output 0 (S = 0, R = 1, = 0) Hold: Keep data stored (S = 0, R = 0, = previous ) SR Latch Symbol R S
8 Add input C Avoiding S=R=1 Part 1: Level-Sensitive SR Latch Change C to 1 only after S and R are stable C is usually a clock (CLK) S Level-sensitive SR latch S1 C R R1
9 D Latch Truth Table CLK D R R D S S CLK D 0 X D X 1 0 S R 0 0 prev prev 1 0
10 D Latch Summary Two inputs: CLK, D CLK: controls when the output changes D (the data input): controls what the output changes to Function When CLK = 1, D passes through to (transparent) When CLK = 0, holds its previous value (opaque) (Mostly) avoids invalid case = D Latch Symbol D CLK
11 D Latch Truth Table CLK D R R D S S CLK D 0 X D X 1 0 S R 0 0 prev prev 1 0
12 D-Latch 12
13 The D flip-flop 13
14 Latches versus flip-flops 14
15 The master-slave D 15
16 Bit Storage Overview SR latch S (set) R (reset) Level-sensitive SR latch S S1 C R R1 D C S R D latch D Clk D latch Dmm Cm master D flip-flop D latch Ds s Cs s servant S=1 sets to 1, R=1 resets to 0. Problem: SR=11 yield undefined. S and R only have effect when C=1. We can design outside circuit so SR=11 never happens when C=1. Problem: avoiding SR=11 can be a burden. SR can t be 11 if D is stable before and while C=1, and will be 11 for only a brief glitch even if D changes while C=1. Problem: C=1 too long propagates new values through too many latches: too short may not enable a store. Only loads D value present at rising clock edge, so values can t propagate to other flipflops during same clock cycle. Tradeoff: uses more gates internally than D latch, and requires more external gates than SR but gate count is less of an issue today. 16
17 Rising vs. Falling Edge D Flip-Flop The triangle means clock input, edge triggered D Symbol for rising-edge triggered D flip-flop rising edges Clk D Symbol for falling-edge triggered D flip-flop Clk falling edges Internal design: Just invert servant clock rather than master 17
18 Enabled D-FFs Inputs: CLK, D, EN The enable input (EN) controls when new data (D) is stored Function EN = 1: D passes through to on the clock edge EN = 0: the flip-flop retains its previous state EN Internal Circuit CLK Symbol D 0 1 D D EN
19 Additional D-FF Features Reset (set state to 0) R synchronous: Dnew = R' Dold (when next clock edge arrives) asynchronous: doesn't wait for clock Preset or set (set state to 1) S (or sometimes P) synchronous: Dnew = Dold + S (when next clock edge arrives) asynchronous: doesn't wait for clock Both reset and preset Dnew = R' Dold + S (set-dominant) Dnew = R' Dold + R'S (reset-dominant) Selective input capability (input enable or load) LD or EN multiplexor at input: Dnew = LD' + LD Dold load may or may not override reset/set (usually R/S have priority) 19
20 Registers and Counters 20
21 Building blocks with FFs: Basic Register Register: a sequential component that can store multiple bits A basic register can be built simply by using multiple D-FFs OUT1 OUT2 OUT3 OUT4 CLK D D D D IN1 IN2 IN3 IN4 I3 I2 I1 I0 reg(4)
22 Shift register Holds & shifts samples of input OUT1 OUT2 OUT3 OUT4 IN D D D D CLK 22
23 Pattern Recognizer Combinational function of input samples OUT OUT1 OUT2 OUT3 OUT4 IN D D D D CLK 23
24 Counters Sequences through a fixed set of patterns Note: definition is general For example, the one in the figure is a type of counter called Linear Feedback Shift Register (LFSR) OUT1 OUT2 OUT3 OUT4 IN D D D D CLK 24
25 General Counters Default operation: count up A-D counter output A-D parallel load data LOAD enables data load RCO ripple carry out CLR clears data EN counter enable "1" "0" "1" "1" "0" "0" EN RCO D D C C B B A A LOAD CLK CLR Similar signals can also be used for registers You can generalize these ideas to build multifunction registers/shifters/counters with a variety of control signals (load, clear, enable, etc.) "1" "0" "0" "0" "0" EN RCO D D C C B B A A LOAD CLK CLR 25
26 Finite State Machines 26
27 Circuit Specifications Combinational Logic Truth tables, Boolean equations, logic diagrams (no feedback) Sequential Networks: State Diagram (Memory) State and Excitation Tables Characteristic Expression Logic Diagram (FFs and feedback loops) Y A B C D Combinational X CLK CLK RTL: Register-Transfer Level Description CLK 27
28 Finite State Machines: Two Bit Counter Example Symbol/ Circuit 2 bit Counter Current state S 0 S 1 S 1 S 2 S 2 S 3 S 3 S 0 Next State For example: S0: Breakfast S1: Lunch S2: Dinner S3: Sleep For example: Count up to 11 S 0 S 3 S 1 1 (t) 0 (t) 1 (t+1) 0 (t+1) S State Diagram State Table
29 1 (t) 0 (t) 1 (t+1) 0 (t+1)
30 Which is the most likely circuit realization of the two bit counter? State Table 1 (t) 0 (t) 1 (t+1) 0 (t+1) A. Combinational circuit Circuit with no flip flops B. C. 0 (t) Combinational circuit 1 (t) D D CLK 0 (t) 1 (t) Combinational circuit D CLK Circuit with 2 flip flops Circuit with one flip flop
31 Two Bit Counter Circuit State Table 1 (t) 0 (t) 1 (t+1) 0 (t+1) D 0 (t) 0 (t) D 1 (t) 1 (t) D D CLK We store the current state using D-flip flops so that: Inputs to the combinational circuit don t change while the next output is computed The transition to the next state only occurs at the rising edge of the clock D 0 (t) = 0 (t) D 1 (t) = 0 (t) 1 (t) + 0 (t) 1 (t) Implementation of 2-bit counter
32 FSM Definition FSM consists of Set of states Set of inputs, set of outputs Initial state I a b A B Set of transitions Only one can be true at a time FSM representations: State diagram State table 32
33 FSM Controller Design Process with a Three Bit Counter Example 1. State Diagram 2. State Table State Assignments Excitation Table (present state, inputs; next state, outputs) 5. Circuit State Table with Assigned State Patterns C3 C2 C1 N3 N2 N CLK "1" bit up-counter FSM 110 Circuit D D D 100 OUT1 OUT2 OUT3 33
34 Mealy and Moore Machines x(t) Mealy Machine Moore Machine C1 C2 y(t) x(t) C1 C2 y(t) CLK S(t) y i (t) = f i (X(t), S(t)) Output is the function of the present state as well as the input! CLK y i (t) = f i (S(t)) S(t) Output is the only function of current state ONLY!
35 What s this state machine? A. Mealy State machine B. Moore state machine C. Can be both D. I don t know 35
36 Life on Mars? Mars rover has a binary input x. When it receives the input sequence x(t-2, t) = 001 from its life detection sensors, it means that the it has detected life on Mars and the output y(t) = 1, otherwise y(t) = 0 (no life on Mars). This pattern recognizer should have A.One state because it has one output B.One state because it has one input C.Two states because the input can be 0 or 1 D.More than two states because. E.None of the above 36
37 Mars Life Recognizer FSM Which of the following diagrams is a correct Mealy solution for the 001 pattern recognizer on the Mars rover? 1/1 A. 1/0 S0 0/0 S1 0/0 S2 0/0 1/0 B. 1/0 0/0 S0 0/0 S1 1/1 S2 1/0 C. Both A and B are correct 0/0 D. None of the above 37
38 State Diagram => State Table with State Assignment 1/1 x(t) 1/0 S0 0/0 1/0 S1 0/0 S2 0/0 C1 C2 CLK S(t) Mealy Machine y(t) S(t)\x 0 1 S0 S1,0 S0,0 S1 S2,0 S0,0 S2 S2,0 S0,1 State Assignment S0: 00 S1: 01 S2: 10 S(t)\x ,0 00, ,0 00, ,0 00,1 1 (t+1) 0 (t+1), y 38
39 State Diagram => State Table => Excitation Table => Circuit 1 (t) 0 (t)\x ,0 00, ,0 00, ,0 00,1 x(t) C1 C2 CLK S(t) Mealy Machine y(t) id 1 0 x D 1 D 0 y X X X X X X 39
40 State Diagram => State Table => Excitation Table => Circuit id 1 0 x D 1 D 0 y X X X X X X D1(t): x(t) X X 0 D1(t) = x 0 + x 1 D0 (t)= 1 0 x y= 1 x 1 40
41 State Diagram => State Table => Excitation Table => Circuit 1 0 x x 0 D0 D1 D D 0 1 y 1 x x(t) D1(t) = x 0 + x 1 D0 (t)= 1 0 x y= 1 x C1 C2 CLK S(t) Mealy Machine y(t) 41
42 Moore Mars Life Recognizer: Summary 1 S0 0 0 S S S3 1 1 S(t)\x 0 1 S0 S1,0 S0,0 S1 S2,0 S0,0 S2 S2,0 S3,0 S3 S1,1 S0,1 1 0 \x ,0 00, ,0 00, ,0 11, ,1 00,1 1 (t+1) 0 (t+1), y 0 ID 1 0 x D 1 D 0 y
43 Mars Life Recognizer: Summary id 1 0 x D 1 D 0 y D1(t): D0(t): y(t): x(t) x(t) x(t) Sources: TSR, Katz, 1 Boriello & Vahid
44 44
45 CSE140: Components and Design Techniques for Digital Systems Review questions 45
46 Example 1: Multiplexers Derive each intermediate signal as a function of a, b, c and d b 00 4:1 MUX a c 1 w s d out c z 11 s1 s0 b d
47 Example 2: Multiplexers Implement the following function using a 4:1 MUX F(a,b,c) = a b c + a(bc +bc )
48 Example 3: Decoders Derive each intermediate signal as a function of a, b, and c 3:8 Decoder a c a b w A0 A1 A2 A0 A1 A s z out
49 Example 4: Decoders Implement the following function using a 3:8 Decoder F(a,b,c) = abc + a(b c +bc ) 49
50 Multiple-Output Circuits Many circuits have more than one output Can give each a separate circuit, or can share gates Ex: F = ab + c, G = ab + bc Option 1: Separate circuits Option 2: Shared gates 50
51 Primes and Essential Primes Given the following function: F(A,B,C,D) = m(0,2,6,7,8,10) + d(1,11,12,15) a) List all prime implicants b) Identify the essential prime implicants c) Give min cover in SoP (Sum-of-Product) form A D C B 51
52 F(A,B,C,D)= Π M(2, 3, 6, 8, 9, 12, 13, 14) K-maps and Muxes A D C B 52
53 Mux/Demux 53
54 Design problem distance between numbers Design a circuit that gives the absolute distance between the two numbers (e.g. x=3 y=1 d=2) 54
55 NAND gates implementation 55
56 Decoder Implement F(A,B, C) = A C + AC with a minimum size circuit. You may use a 2:4 decoder and minimum number of other gates. 56
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