Digital Logic Design. Midterm #2

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1 EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm - igital Logic esign Midterm #2 Problems Points Total 5 Was the exam fair? yes no

2 EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm - 2 Problem 5 points Given is the logic circuit model of a state machine shown in Figure.. y y + (y +) J K J Q FF K Q C y y Z y y + y (y + ) J 2 K 2 J Q FF2 K Q C J = (y +) J 2 = y (y + ) K = K 2 = Z = y Figure. state machine with two flip-flops in its internal state memory block. Logical model of the circuit. erived excitation functions of the internal state memory flip-flops and the output function z...5 Using the given logical model of Figure., demonstrate an ability to:. determine the expressions of logic functions at the outputs of all logic gates in the combinational block of the logical model; 2. apply the knowledge of Boolean algebra to the simplification of logic functions; 3. recite the characteristic function of the JK-type flip-flop, and compose expressions of the state transition excitation functions of the internal memory block; 4. derive the content of the State Transition Table from the Next State Functions, 5. draw the State Transition Graph based on the known State Transition Table. Hint # For full credit: all equations, all answers to questions, all circuit models and other graphical representations are expected to be entered into the space designated for them; all shown numerical results must be preceded by the symbolic and numeric expressions whose evaluation produces the results. Solution n explicit demonstration of understanding the following solution steps is expected. Next to the outputs of logic gates in the circuit of Figure., indicate the expressions of logic gates output functions. Write in the space reserved for Figure. the expressions of the

3 EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm - 3 excitation functions of internal memory flip-flops and the expression of the output function Z..2 In the space reserved for equation (-).5 Characteristic Function. fill in the expression of the JK-type flip-flop s Y i = J i y i + K i y i (-).3 In the space reserved for equations (-2) through (-6), fill in the simplified expressions of the flipflops excitation functions of the internal state memory (flip-flops), and the output Z. J = (+y ) (-2) J 2 = y (y + ) = y (-4) K = (-3) K 2 = (-5) Z = y (-6).4 In the space reserved for equations (-7) and (-8), fill in the simplified expressions of the State Transition Functions of the internal state memory flip-flops. Y = J y +K y = (+y ) y + y = y +y + y = y + y (-7) Y 2 = J 2 + K 2 = y + = (-8).5.6 In the space reserved for Figure.2, fill in the contents of the State Transition Table of the State Machine of the logic circuit model of Figure.. In the space reserved for Figure.2, prepare the drawing of the State Transition Graph (state diagram) of the State Machine of the logic circuit model of Figure.. y / / / / / / / /,/ / / / / Y Y 2 /z / / Figure.2 Results of the analysis. State Transition Table of the SM from Figure.. State Transition Graph (State diagram) of the SM from Figure..

4 EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm - 4 Problem 2 4 points Given is a logic function F 2 in the decimal sum of minterms representation (2-). F 2 (,B,C,) = Σ(,, 4, 6, 8,, 4, 5) (2-) 2 Problem Statement For the logic function (2-), demonstrate an ability to:. design a combinational circuit which uses an 8: multiplexer module to implement the function (2-), 2. apply the design method which is based on preparation of either one of the following two tables: - MUX Implementation Table, or - Truth Table of the function to be implemented. Hint # For full credit: all equations, all answers to questions, all circuit models and other graphical representations are expected to be entered into the space designated for them; all shown numerical results must be preceded by the symbolic and numeric expressions whose evaluation produces the shown results. Problem Solution n explicit demonstration of understanding the following solution steps is expected. 2. epending on the selected design method, fill in the missing data in either the MUX Implementation Table of Figure 2., or the Truth Table of Figure 2.2. I I I 2 I 3 I 4 I 5 I 6 I MUX 8: s 2 s s F 2 (,B,C,) B C Figure 2. MUX Implementation Table method. MUX implementation table. Implementation of the function (2-).

5 2 s7m2s_dild7.fm - 5 The University of Toledo EECS: igital Logic esign r. nthony. Johnson 2.2 Consistent with the selected design method, show in the space reserved for Figure 2., or alternatively in the space reserved for Figure 2.2, how the logical constants and, and the literals of the logical variables, B, C, and ought to be applied to the MUX module s inputs. Figure 2.2 Truth Table method. Truth table. Implementation of the function (2-) s 2 s s MUX 8: F(,B,C,) B C B C F I k k=(s 2 s s ) 2,, 4, 6, 8,, 4, 5)

6 EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm - 6 Problem 3 6 points Given is the following verbal specification of a state machine (SM): the SM has one input signal S, the SM has one output signal Z, (c) the SM recognizes the input signal sequence, (d) every time the input signal sequence has been observed by the SM, the output signal Z is to be set to Z =, otherwise Z =; (overlapping sequences are to be recognized). (e) the SM is to be implemented using positive edge triggered -type flip-flop(s). S Next state logic I N Q n / Internal state memory Y y n / I Output logic O y Z Figure 3. General architecture of a Mealy type State Machine. Problem Statement Based on the given verbal specification, demonstrate an ability to:. compose the graphical representation of the State Transition Graph of a state machine that will implement the given verbal specification of the SM, 2. compose a State Transition Table which describes the same State Machine as already described by the composed State Transition Graph, 3. combine the information from the State Transition Table and the flip-flop s Excitation Table to prepare the State Transition Excitation Table of the specified SM. 4. apply the Karnaugh Map simplification method to derive the internal state excitation functions described in the Transition Excitation Table of the specified SM, 5. compose a minimum number of logic gates circuit which implements the State Machine for which the internal state memory is specified, and for which the flip-flop excitation functions have been derived. Hint # For full credit: all equations, all answers to questions, all circuit models and other graphical representations are expected to be entered into the space designated for them; all shown numerical results must be preceded by the symbolic and numeric expressions whose evaluation produces the shown results.

7 EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm - 7 Problem Solution n explicit demonstration of understanding the following solution steps is expected. 3. ssigning to the initial state the binary encoded name "", prepare a graphical representation of the State Transition Graph of the SM which will implement the given verbal specification. Show the prepared State Transition graph in the space reserved for Figure In the space reserved for Figure 3.2 fill in the contents of the State Transition Table that corresponds to the prepared state transition graph. 3.3 In the space reserved for Figure 3.2(c) fill in the contents of the Excitation Table of a -type flipflop. 3.4 In the space reserved for Figure 3.2(d), compose the State Transition Excitation Table of the SM by combining the information from the state transition table of the SM and the excitation table of the flip-flop Using the Karnaugh map method, derive the simplified expressions of the flip-flop excitation function(s), 2 and the output function Z, and manipulate them into expressions with minimum number of literals. Show the obtained expressions into the space reserved for Figure 3.2(f). y y? 2 S y Y Y 2 2 Z? S / / / / dd/ / / / dd/ / / Y d d d d Y 2 /Z y Y / / d d d d (d) (c) / Sy d Sy d Sy = Sy + S = = S(y + ) d d 2 = Sy (e) - Kmap 2 - Kmap Z- Kmap Z = Sy Figure 3.2 esign process of the State Machine. State transition graph of the SM. State transition table of the SM. (c)-type flip-flop excitation table. (d)state Transition Excitation table of the SM (e)karnaugh maps of the functions, 2, and Z. (f) Simplified expressions of logic functions, 2 and Z. (f)

8 EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm In the space reserved for Figure 3.3 prepare the minimum number of logic gates logical circuit model which implements the State Machine whose specification is given at the beginning of this problem. y + S Y Q y Q FF y S Z=Sy = Sy + S = Y 2 Q FF2 Q = S(y + ) 2 = Sy Z = Sy Figure 3.3 Logical circuit model of the State Machine that implements the recognizer of the input sequence.

Digital Logic Design. Midterm #2

Digital Logic Design. Midterm #2 EECS: igital Logic esign r. nthony. Johnson f5m2s_il7.fm - igital Logic esign Miterm #2 Problems Points. 5 2. 4 3. 6 Total 5 Was the exam fair? yes no EECS: igital Logic esign r. nthony. Johnson f5m2s_il7.fm