3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value

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1 EGC22 Digital Logic Fundamental Additional Practice Problems. Complete the following table of equivalent values. Binary. Octal Hexadecimal B.3 D.FD B.4C 2. Calculate the following a) () 2 plus () 2 = b) 2 minus 2 using 2 s complement representation = c) _2 times _2 =_ 3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value Decimal Unsigned Signed Magnitude Signed 2 s Complement (a) Explain the difference between a Moore machine and a Mealy machine. Sol The outputs in a Moore machine depend only on the present state. The outputs in a Mealy machine depend on both the present state and the present input. (b) What is the same about both kinds of state machines? Sol Both have present state dependent on past inputs. (c) Draw a block diagram indicating the structure of a general state machine. Indicate on the diagram where one can find the present state and next state. X Next State Logic y Flip Flops Y Logic Z

2 A _B _C EGC22 Digital Logic Fundamental Additional Practice Problems 5. Give a truth table and a standard sum of products expression that describes F = _ A B C F F = AB \ C \ +A \ B \ C +A \ BC \ +ABC 6. Indicate how a N gate can be used to implement: 5V (a) An Inverter: X X or could do X X (b) An And Gate: A B X (c) An Or Gate: X = A + B = (A B ) A X

3 EGC22 Digital Logic Fundamental Additional Practice Problems 7. Using the 74ALS63 counter shown below and logic gates design a counter that counts in the sequence 3,4, 5, 6, 7, 8, 9,,, 2, 3,... Connect all unused inputs. The counter may cycle through several unwanted states before settling into the final count sequence. Q d is the MSB of the counter output. 74S63 CLK 8. Find a minimum sum of products expression for F = abc \ +bc \ d \ +cd +a \ b f cd ab F = a b + cd + bc

4 EGC22 Digital Logic Fundamental Additional Practice Problems 9. Create a state diagram for a sequence detector that outputs a when it detects the final bit in the serial data stream. Assume overlapping is allowed. Mealy Machine Moore Machine X/Z / S / S / S2 S3 =

EGC22 Digital Logic Fundamental Additional Practice Problems. Determine the D flip-flop equations for the system represented with in the state- transition table below.

5 EGC22 Digital Logic Fundamental Additional Practice Problems. Determine the D flip-flop equations for the system represented with in the state- transition table below. Assign states: S =, S =, S2 = and S3 =. Da AB X Present Present Next State Output AB S X= X= Z S S S2 S S S2 S2 S2 S3 S3 S3 S Da = X A + XA + { AB XB Db AB X. Give the output expression for the 8-to- MUX shown below. Db = XAB + X A + X B IO I I2 I3 I4 I5 I6 I7 8 to MUX z A B C Z = A \ B \ C \ I +A \ B \ CI +A \ BC \ I2 +A \ BCI3 +AB \ C \ I4 +AB \ CI5 +ABC \ I6 +ABCI7

6 2. Finite State Machines: Sequence Recognizer You want to build a finite state machine that will recognize the sequence x = and output the sequence z = as this sequence occurs. In other words, output z = when first receiving x =. Then output z = if the next bit of x = ; output z = again if the following bit of x =. Finally, if the last (fourth) bit of x =, output z =. More simply, output z = until the sequence x = is received, at which time output z =. (a). First, draw and label the transitions in the state bubble diagram below. The states are already labeled (but state bit values have not been assigned). Allow overlap of sequences. Build as a Moore machine. Include the input bits of x and output bits of z. Solution: x= START z= x= x= GOT x= x= x= x= GOT x= GOT x= x= GOT Note: This sequence recognizer allows for overlap of sequences, and thus outputs z = whenever the sequence x = is recognized with overlap of sequences. If we do not allow for overlap, then the transitions from state GOT will go to state START for both x = and x =. Without overlap, whenever the sequence x = is input, the output will be z =. 2(b). Write the state table from the state bubble diagram. Fill in the table given below. Use the following state assignments: START=, GOT=, GOT=, GOT= and GOT=. All unused states should go to the START state and output z =. Assume you will build the circuit with J-K flip-flops. Solution: (next page)

7 2 Present State Input Output Next State Flip-Flop Inputs Q 2 Q Q x z Q 2 Q Q J 2 K 2 J K J K X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 2(c). Find the minimized logic equations for output z and flip-flop inputs J 2, K 2, J, K and J, K ; use K-maps if needed. Solution: Output z: Output z can be determined directly from the truth table, as z = only when Q 2 =, Q = and Q =. Therefore, z = Q 2 Q Q. You may check with a K-map if you prefer. z = Q 2 Q Q K-map for J 2 : Q x Q 2 Q X X X X X X X X

8 3 From the K-map above, we obtain the following expression for J 2 : J 2 = Q Q x K 2 : Note that K 2 is either X or for every entry of the truth table. Therefore, we may set K 2 =. K 2 = K-map for J : Q x Q 2 Q X X X X X X X X From the K-map above with two groupings, we obtain the following expression for J : J = Q 2 Q x + Q 2 Q x This expression may be further simplified by recognizing that Q 2 Q + Q 2 Q = Q 2 Q ; J = x(q 2 Q ) K-map for K : Q x Q 2 Q X X X X X X X X From the K-map above with three groupings, we obtain the following expression for K : K = Q + Q 2 + x

9 4 K-map for J : Q x Q 2 Q X X X X X X X X From the K-map above with two groupings, we obtain the following expression for J : J = Q x + Q 2 Q K-map for K : Q x Q 2 Q X X X X X X X X From the K-map above with three groupings, we obtain the following expression for K : K = Q + Q 2 + x 2(d). outputs. Draw the corresponding circuit diagram with J-K flip-flops. Label all inputs and Solution: (next page) Note: The black dots in the figure indicate a connection between wires. If there is no black dot, there is no connection between wires that cross.

5 x NOT XOR +5V CLK J 2 K 2 Q 2 Q 2 J K Q J Q K Q Q OR OR OR z 3. State Diagram of Mealy Machine Redraw the state diagram using a Mealy machine design. Be sure to label the transitions and bubbles.

10 5 x NOT XOR +5V CLK J 2 K 2 Q 2 Q 2 J K Q J Q K Q Q OR OR OR z 3. State Diagram of Mealy Machine Redraw the state diagram using a Mealy machine design. Be sure to label the transitions and bubbles. You may name your states whatever you like. Again allow overlap of sequences. How many states and flip-flops do you need for the Mealy design? Solution: x/z=/ START BIT / / x/z=/ /, / BIT3 / / BIT2 Only four states are required for the Mealy machine design. Two state bits are thus needed to determine all the states. This means that only two flip-flops are required to implement the Mealy machine design of the sequence recognizer. 4. Analysis of FSM Circuit Design Below is a simplified block diagram of a heart pacemaker. The output p from the pacemaker pulses high if the heart does not contract within a certain time. The input s indicates whether the heart has contracted (s = ) or not (s = ). The input t comes from a timer,

6 which counts for the expected time between contractions (approximately second). When t =, the timer has counted up to second, and the heart should have contracted.

11 6 which counts for the expected time between contractions (approximately second). When t =, the timer has counted up to second, and the heart should have contracted. If the heart has not contracted within that time, the pacemaker sends a pulse p =. (There is also a timer reset control coming from the pacemaker, which we ignore for this problem.) The inputs to the pacemaker circuit are s (from the heart) and t (from a timer - not shown). The output of the pacemaker circuit is p, which goes to the heart. Arrows indicate the inputs and output. Heart p s NOT s Pacemaker Q D D Q t CLK Q Q OR Note: The black dots in the figure indicate a connection between wires. If there is no black dot, there is no connection between wires that cross. 4(a). Is this a Mealy or a Moore machine? Why? Solution: This is a Mealy machine. The output p depends on the input s, as well as the sequential logic output states Q and Q and the input t from a timer clocked synchronously with FF and FF. This means that the output p can change at times other than on a rising clock edge, if the input s changes. The input s is not clocked, and is not constrained to change only on a rising clock edge. 4(b). Write the equations for output p and the flip-flop inputs D and D from the block diagram. Solution: Output p: p = Q Q s t D input for Flip-flop, D : D = p = Q Q s t

12 7 D input for Flip-flop, D : D = Q Q + Q s 4(c). Solution: Fill in the state table below, using the equations obtained in part 3(b). Present State Inputs Output Next State Q Q s t p Q Q

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final