Chapter 7. Synchronous Sequential Networks. Excitation for

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1 Chapter 7 Excitation for Synchronous Sequential Networks J. C. Huang, 2004 igital Logic esign 1 Structure of a clocked synchronous sequential network Mealy model of a clocked synchronous sequential network Excitation for J. C. Huang, 2004 igital Logic esign 2 J. C. Huang, 2004 igital Logic esign 3 Moore model of a clocked synchronous sequential network Logic diagram for Example 7.1 J. C. Huang, 2004 igital Logic esign 4 J. C. Huang, 2004 igital Logic esign 5

2 Logic diagram for Example 7.2 State diagram for Example 7.1 J. C. Huang, 2004 igital Logic esign 6 J. C. Huang, 2004 igital Logic esign 7 State diagram for Example 7.2 Timing diagram for Example 7.1 J. C. Huang, 2004 igital Logic esign 8 J. C. Huang, 2004 igital Logic esign 9 The analysis procedure The serial binary adder J. C. Huang, 2004 igital Logic esign 10 J. C. Huang, 2004 igital Logic esign 11

3 Obtaining the diagram for a Mealy serial binary adder. (a) Partial diagram. (b) Completed diagram. Reset ( ab s ) G H G: H: 00 1 carry-in = 0 carry-in = 1 State diagram for the serial adder J. C. Huang, 2004 igital Logic esign 12 J. C. Huang, 2004 igital Logic esign 13 Present Next Output s ab = a b Full adder Y carry-out Q y s G G G G H H G H H H 1 1 Clock Q Reset State table for the serial adder Circuit for the adder FSM J. C. Huang, 2004 igital Logic esign 14 J. C. Huang, 2004 igital Logic esign 15 State diagram for a Moore serial binary adder Reset 00 G 0 s = 0 11 H 0 s = G 1 s = 1 00 H 1 s = 1 11 State diagram for the Moore-type serial adder FSM J. C. Huang, 2004 igital Logic esign 16 J. C. Huang, 2004 igital Logic esign 17

4 A Present Next Output ab = s G 0 G 0 G 1 G 1 H G 1 G 0 G 1 G 1 H 0 1 H 0 G 1 H 0 H 0 H 1 0 H 1 G 1 H 0 H 0 H 1 1 Clock Shift register Shift register a b Adder FSM s Shift register Sum = A + State table for the Moore-type serial adder FSM lock diagram of a serial adder J. C. Huang, 2004 igital Logic esign 18 J. C. Huang, 2004 igital Logic esign 19 A sequence recognizer State diagram for a sequence recognizer. (a) etection of two consecutive 0 s. (b) Partial analysis of the three-symbol sequence. (c) Completed diagram. (d) efinition of s. J. C. Huang, 2004 igital Logic esign 20 J. C. Huang, 2004 igital Logic esign 21 A 0110/1001 sequence recognizer. (a) eginning the detection of the sequences 0110 or (b) efinition of s. (c) Completing the detection of the two sequences 0110 or (d) Completed diagram. State diagram for the final example J. C. Huang, 2004 igital Logic esign 22 J. C. Huang, 2004 igital Logic esign 23

5 State reduction Experiment for determining equivalent pairs of s Theorem 7.1 Two s p and q of a synchronous sequential network are equivalent if and only if for each combination of values of the input variables (1) their outputs are identical and (2) their next s are equivalent. J. C. Huang, 2004 igital Logic esign 24 J. C. Huang, 2004 igital Logic esign 25 The structure of an implication table Implication table inspection process If (q a,q b ) is in the q i q j cell, and if q a q b cell contains a, then place a in the q i q j cell and ignore all other entries in that cell. Otherwise inspect other pairs in q i q j. Repeat this steps until it is possible to make an entire pass without adding a new. Upon completion, if q i q j cell contains no then q i is equivalent to q j. J. C. Huang, 2004 igital Logic esign 26 J. C. Huang, 2004 igital Logic esign 27 A C E F G Example table next x=0 x=1 A C F E F G G C A F output (z) x=0 x= Implication table for determining the equivalent s. (a) The initial table. (b) After the first pass. (c) After the second pass. J. C. Huang, 2004 igital Logic esign 28 J. C. Huang, 2004 igital Logic esign 29

6 Equivalence classes of s The resulting implication table shows that A=, A=G, =F, and =G. This leads us to the formation of the equivalence classes {(A,,G), (,F), (C), (E)} Hence the reduced table shown below. (A,,G): α (,F): β (C): γ (E): δ Minimized example table next x=0 x=1 α β α γ β δ β α output (z) x=0 x=1 0 1 J. C. Huang, 2004 igital Logic esign 30 J. C. Huang, 2004 igital Logic esign 31 Implication table for determining equivalent s of the 0110/1001 sequence recognizer. (a) Initial table. (b) Final table. Logic diagram for the excitation table of Table 7.19 J. C. Huang, 2004 igital Logic esign 32 J. C. Huang, 2004 igital Logic esign 33 Logic diagram for the excitation table of Table 7.20 Logic diagram for the Moore serial binary adder J. C. Huang, 2004 igital Logic esign 34 J. C. Huang, 2004 igital Logic esign 35

7 inputs combinational circuit outputs memory elements Typical block diagram of a sequential circuit J. C. Huang, 2004 igital Logic esign 36 Example sequential circuit 1 J. C. Huang, 2004 igital Logic esign 37 x comb. network A=A +x y = x =x(a + ) + x A ' A' A lock diagram of Example 1 Example sequential circuit 2 J. C. Huang, 2004 igital Logic esign 38 J. C. Huang, 2004 igital Logic esign 39 x comb. network A=xA+x =xa' y = (A+)x' ' A' A lock diagram of Example 2 J. C. Huang, 2004 igital Logic esign 40 Example sequential circuit 3 J. C. Huang, 2004 igital Logic esign 41

8 x comb. network ' A' A J K J K JA = KA = x' J = x' K = A'x + Ax' KA JA K J lock diagram of Example 3 next x = 0 x = 1 A(t)(t) A(t+1)(t+1)? A(t+1)(t+1)? 0 1?? 1 0?? 1 1?? To analyze the preceding circuit is to complete this table J. C. Huang, 2004 igital Logic esign 42 J. C. Huang, 2004 igital Logic esign 43 Steps involved: 1. Construct the truth table of the combinational network to determine the output and the input to the flip-flops. 2. Use the characteristic table of the flip-flops to determine the next s. x comb. network ' A' A J K J K JA = KA = x' J = x' K = A'x + Ax' KA JA K J Sequential circuit implemented with JK flip-flops (Fig. 6-19) J. C. Huang, 2004 igital Logic esign 44 J. C. Huang, 2004 igital Logic esign 45 Step 1: construct the truth table of the combinational network. x A JA KA J K Step 2: extend the truth table to inclues contents of flip-flops at time t+1. x A JA KA J K A(t+1) (t+1) J. C. Huang, 2004 igital Logic esign 46 J. C. Huang, 2004 igital Logic esign 47

9 Step 2.1: find A(t+1), with the help of a characteristic table. x A JA KA J K A(t+1) (t+1) Step 2.2: find (t+1), with the help of a characteristic table. x A JA KA J K A(t+1) (t+1) The characteristic table of a JK flip-flop J K Q(t+1) Q(t) no change reset set 1 1 Q'(t) complement The characteristic table of a JK flip-flop J K Q(t+1) Q(t) no change reset set 1 1 Q'(t) complement J. C. Huang, 2004 igital Logic esign 48 J. C. Huang, 2004 igital Logic esign 49 Step 2.3: final step. x A JA KA J K A(t+1) (t+1) Reconstruct the table to yield next x = 0 x = 1 A(t)(t) A(t+1)(t+1) 0 1 A(t+1)(t+1) J. C. Huang, 2004 igital Logic esign 50 Mealy and Moore Models There are two models of sequential circuit: Mealy Model: the outputs are functions of both the s and inputs. Moore Model: the outputs are a function of the only. Example: J. C. Huang, 2004 igital Logic esign 51 esign Steps State Reduction Two s are said to be equivalent if, for each possible single input, they giv e exactly the same output and send the circuit either to the same or to an equivalent. When two s are equivalent in this sense, one of them can be removed without altering the input-output relations. 1. Obtain the word description of the desired circuit behavior. 2. Construct the table of the desired circuit. 3. Reduce the numb er of to the extent possible ( reduction). 4. Assign a bit pattern to each ( assignment). 5. etermine the no. of flip-flops needed and assign a letter symbol to each. 6. Choose the type of flip-flop to be used. 7. erive the truth table of the required combinational circuit from the table. 8. Simplify the combinational circuit. 9. raw the logic diagram. J. C. Huang, 2004 igital Logic esign 52 J. C. Huang, 2004 igital Logic esign 53

10 e sign Ex ampl e: Suppo se we are given a w ord descript ion of th e d es ired cir cuit behavio r, and it is translated into the fol low ing table (Step 2): presen t nex t sta te outpu t x=0 x=1 x=0 x=1 a f b b d c c f e d g a 1 0 e d c f g d 0 1 g g h 0 1 h g a 1 0 J. C. Huang, 2004 igital Logic esign 54 State reduction (step 3) next output x=0 x=1 x=0 x=1 a f b b d a c c f b e d f g a 1 0 e d a c f f g d 0 1 g g d h 0 1 h g a 1 0 J. C. Huang, 2004 igital Logic esign 55 esign Example: A possible assignment (State 4): The reduced table (Step 3): next output x=0 x=1 x=0 x=1 a f b b d a d f a 1 0 f f d 0 1 next output x=0 x=1 x=0 x=1 a f b b d a d f a 1 0 f f d 0 1 a b d 11 f next output x=0 x=1 x=0 x=1 A A(t+1)(t+1) A(t+1)(t+1) y(t) y(t) J. C. Huang, 2004 igital Logic esign 56 J. C. Huang, 2004 igital Logic esign 57 esign Example This table can be implemented by a sequential circuit of the form depi cted below using type flip-flops (Steps 5 and 6): x comb. network A=? =? y=? Reconstruct the table next output x=0 x=1 x=0 x=1 A A(t+1)(t+1) 1 1 A(t+1)(t+1) 0 1 y(t) 0 y(t) ' A' A J. C. Huang, 2004 igital Logic esign 58 J. C. Huang, 2004 igital Logic esign 59

11 in preparation for expanding it into a truth table of the combinational network required (Step 7): x A(t) (t) A(t+1) (t+1) y(t) J. C. Huang, 2004 igital Logic esign 60 Expand the table into the truth table of the combinational network (Step 7): x A(t) (t) A(t+1) (t+1) A y(t) Excitation table of a type flip-flop Q(t) Q(t+1) (t) J. C. Huang, 2004 igital Logic esign 61 Expand the table into the truth table of the combinational network (Step 7): Excitation vs. application table An excitation table is a table that shows what inputs are needed to make the flipflops to change the s as desired. An application table is an excitation table constructed for a particular type of flip-flop. J. C. Huang, 2004 igital Logic esign 62 x A(t) (t) A(t+1) (t+1) A y(t) Excitation table of a type flip-flop Q(t) Q(t+1) (t) J. C. Huang, 2004 igital Logic esign 63 Simplify the oolean functions that describe the outputs of the combinational network (Step 8): esign Example A'' A' A A' x' This table can be implemented by a sequential circuit of the form depi cted below using JK flip-flops (Steps 5 and 6): x 1 0 A = x' + A A'' A' A A' x' x 1 0 = x'a + A'' x comb. network KA=? JA=? K=? J=? y=? A'' A' A A' x' 0 1 x 1 0 y = x'a' + xa ' A' A J K J K J. C. Huang, 2004 igital Logic esign 64 J. C. Huang, 2004 igital Logic esign 65

12 Again, start with the table: x A(t) (t) A(t+1) (t+1) y(t) In preparation for constructing the truth table of the required combinational circuit, expand the table to include the columns for inputs to the flip-flops: x A(t) (t) A(t+1) (t+1) JA KA J K y(t) J. C. Huang, 2004 igital Logic esign 66 J. C. Huang, 2004 igital Logic esign 67 With the help of an excitation table find inputs to flip-flop A (Step 7): x A(t) (t) A(t+1) (t+1) JA KA J K y(t) X X X X X X X X 0 1 Excitation table of a JK flip-flop Q(t) Q(t+1) J(t) K(t) 0 X X 1 0 X X 0 J. C. Huang, 2004 igital Logic esign 68 With the help of an excitation table find inputs to flip-flop (Step 7): x A(t) (t) A(t+1) (t+1) JA KA J K y(t) X 1 X X X X 0 1 X X 0 X X 1 X X X X 1 0 X X 0 X 1 1 Excitation table of a JK flip-flop Q(t) Q(t+1) J(t) K(t) 0 X X 1 0 X X 0 J. C. Huang, 2004 igital Logic esign 69 A'' A' A A' Simplify the output s of the combinational network (Step 8): A'' A' A A' x' 1 1 X X x X X JA = x' A'' A' A A' x' X X x X X 0 1 KA = x' x' 1 X X 1 x 1 X X 0 J = x' + A' A'' A' A A' x' X 1 0 X x X 1 1 X K = x + A' A'' A' A A' x' 0 1 x 1 0 y = x'a' + xa J. C. Huang, 2004 igital Logic esign 70 J. C. Huang, 2004 igital Logic esign 71

13 esign of a 4-bit synchronous up counter The table (at time t) next (at t+1) The block diagram KA 4 A 4 A 3 A 2 A 1 A 4 A 3 A 2 A combinational network JA 1 A 1 J A' 1 K A 2 J A' 2 K A 3 J A' 3 K A 4 J A' 4 K CP J. C. Huang, igital Logic esign 72 J. C. Huang, 2004 igital Logic esign 73 The excitation function for the four JK flip-flops (at time t) A 4 A 3 A 2 A 1 next (at t+1) JA 1 KA 1 JA 2 KA 2 JA 3 KA 3 JA 4 KA 4 A 4 A 3 A 2 A X 0 X 0 X 0 X X 1 1 X 0 X 0 X X X X 0 X X 1 X 1 1 X 0 X X 0 X X X X 1 1 X X X X X 0 X X X 1 X 1 X 1 1 X X 0 X 0 X X X 1 1 X 0 X X X X X X X 1 X 1 1 X X X 0 X X 0 X X 1 1 X X 0 X X X 0 X 0 X X 1 X 1 X 1 X 1 J. C. Huang, 2004 igital Logic esign 74 From the truth table we see that the desired inputs to the flip-flops can be simplified to JA 1 = 1 KA 1= 1 JA 2 = A 1 KA 2= A 1 JA 3 = A 2A 1 KA 3= A 2A 1 JA 4 = A 3A 2A 1 KA 4= A 3A 2A 1 and hence the logic diagram shown in Fig Note that if we let JA 1 = KA 1 = 0 then none of the flip-flop will change its, and therefore we can use it to stop (i.e., to disable) the counter. J. C. Huang, 2004 igital Logic esign 75 esign of a 4-bit synchronous down counter The excitation function for the four JK flip-flops The table next A A A A 1 A A A A 1 (at time t) (at t+1) X 1 X 1 X 1 X A A A A A A A A X 1 0 X 0 X 0 X X X 1 0 X 0 X X 1 X X 0 X X 1 X X 1 0 X X 1 0 X X X X X 1 X X X 1 X 0 X X X 1 X 1 X X X 1 0 X 0 X X X X 1 0 X X X 1 X X X X 1 X X 1 X X 1 0 X X 0 X X X 1 X 0 X X 1 X 0 X 0 X 0 J. C. Huang, igital Logic esign 76 J. C. Huang, 2004 igital Logic esign 77 (at time t) next (at t+1) JA 1 KA 1 JA 2 KA 2 JA 3 KA 3 JA 4 KA 4

14 From the truth table we see that the desired inputs to the flip-flops can be simplified to JA 1 = 1 KA 1= 1 JA 2 = A' 1 KA 2= A' 1 JA 3 = A' 2A' 1 KA 3= A' 2A' 1 JA 4 = A' 3A' 2A' 1 KA 4= A' 3A' 2A' 1 This is reflected in the logic diagram shown in Fig Note that this design can be directly translated into a T flip -flop impl ementation because the J input to every flip-flop is id entical to its K input. esign verification As the last step in design, analyze the resulting circuit to make sure that it realizes the given table. If there are unused s, make sure that none of them have undesirable properties. For example, at a very minimum, none of them should be an isolated. J. C. Huang, 2004 igital Logic esign 78 J. C. Huang, 2004 igital Logic esign 79 Isolated unused s General structure of a clocked sequential network realization using a PL and clocked flip-flops We need to pay attention to the unused because when the power is turned on, or noise interfere, a sequential circuit might enter an unused. If the unused s are isolated, we will not be able to make the circuit to perform useful function. Requirements on unused s differ. J. C. Huang, 2004 igital Logic esign 80 J. C. Huang, 2004 igital Logic esign 81 A clocked synchronous sequential network realization using a PLA and clocked flip-flops J. C. Huang, 2004 igital Logic esign 82 J. C. Huang, 2004 igital Logic esign 83

15 J. C. Huang, 2004 igital Logic esign 84 J. C. Huang, 2004 igital Logic esign 85