Digital Logic Design - Chapter 5

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1 Digital Logic Design - Chapter 5 S. Design a 2-bit binary up counter a) using positive-edge-triggered D flip-flops. b) using positive-edge-triggered T flip-flops. c) using positive-edge-triggered JK flip-flops. a) Step ) Draw a state diagram. After every rising edge clock count increases by one. y y /ZZ Step 2) There are 4 states; therefore we need 2 FFs (2 2 =4) using full encoding Step 3) Assign a unique code for each state. In this case it is the same as the count Step 4) Derive excitation input and external output equations. The output and present state are the same (Moore machine); below is the PS/NS table to derive excitation equation: Present State Next State Part a - D FF D = y + Part b - T FF T=y y + Part c - JK FF J= Y +, K= Y + Y Y Y + Y + D D T T J K J K D-FF Excitation Equations: y y y y D = y y D = y Digital Design Logic page 4

2 Step 5) Schematic: Z Z Q Q D Q D Q b Alternative solution ) Since we already have designed using D flip-flop then use T-FF flip-flop to build a D flip-flop as shown below and use them to implement the circuits with T flip flop. D T Q Q b Alternative solution 2) Steps,2 and 3 are the same regardless of flip-flop type. So start with step 4 for T flip-flop: Step 4) Derive excitation input and external output equations. The output and present state are the same (Moore machine); below is the PS/NS table to derive excitation equation: Present State Y Y Next State Y + Y + Part b - T FF T=y y + T T T-FF Excitation Equations: y y y y T = y T = Digital Design Logic page 42

3 Step 5) Schematic: Z Z Q T Q +5v T Q Q c Alternative solution ) Since we already have designed using D flip-flop, use JK-FF flip-flop to build a D flip-flop as shown below and use them to implement the circuits with JK flip flop. D J Q K Q c Alternative solution 2) Steps,2 and 3 are the same regardless of flip-flop type. So start with step 4 for JK flip-flop: Step 4) Derive excitation input and external output equations. The output and present state are the same (Moore machine); below is the PS/NS table to derive excitation equation: Present State Y Y Next State Y + Y + Part c - JK FF J= Y +, K= Y + J K J K D-FF Excitation Equations: y y y y y y y y J = y y K = (y y ) J = y K = y Digital Design Logic page 43

4 Step 5) Schematic: Z Z J Q J Q Q Q K K U. Design a 2-bit binary down counter a) using positive-edge-triggered D flip-flops. b) using positive-edge-triggered T flip-flops. c) using positive-edge-triggered JK flip-flops. 2S. Design a (Binary Coded Decimal) counter using: a) positive-edge-triggered D flip-flops. b) positive-edge-triggered T flip-flops. c) positive-edge-triggered JK flip-flops. (Steps through 3 of design are independent of the type of FF used.) Step ) Draw a state diagram. Unused States Step 2) There are states; therefore we need 4 FFs (2 4 =6> ) (using full encoding). Step 3) Assign a unique code for each state. (Use the BCD value as the state value.) Step 4) Derive excitation input and external output equations. Note: The output and present state are the same (Moore machine); therefore: Z = Y Z 2 = Y 2 Z 3 = Y 3 Z 4 = Y 4 Present State Next State Part a - D FF D = y + Part b - T FF T=y y + Part c - JK FF J= Y +, K= Y + Y 4 Y 3 Y 2 Y Y + 4 Y + 3 Y + 2 Y + D 4 D 3 D 2 D T 4 T 3 T 2 T J 4 K 4 J 3 K 3 J 2 K 2 J K Digital Design Logic page 44

5 D-FF Excitation Equations: y 4 y3 y 2 y y 2 y y4y3 y 2 y y4y3 y 2 y y4y3 D 4 D 3 D 2 D D 4 = y 4 y 3 y 2 y + y 4 y 3 y 2 y D 3 = y 4 y 3 y 2 y + y 4 y 3 y 2 + y 4 y 3 y D 2 = y 4 y 2 y + y 4 y 2 y D = y 4 y + y 3 y 2 y Step 5) Schematic: Z Z 2 Z 3 Z 4 Clock D Q Q D 2 Q 2 Q 2 D 3 Q 3 Q 3 D 4 Q 4 Q 4 y 4 y 3 y 2 y + y 4 y 3 y 2 y y 4 y 3 y 2 y + y 4 y 3 y 2 + y 4 y 3 y y 4 y 2 y + y 4 y 2 y y 4 y + y 3 y 2 y b) To design using T flip-flop, build a D flip-flop from T- flip-flop as shown below and use it to re-implement the circuit from section a. Digital Design Logic page 45

6 D T Q Q c) To design using JK flip-flop, build a D flip-flop using JK-FF as shown below and use it to re-implement the circuit from section a. D J Q K Q 2U. Design a binary counter that counts from 2 to 7 and then restarts from 2: a) positive-edge-triggered D flip-flops. b) positive-edge-triggered T flip-flops. c) positive-edge-triggered JK flip-flops. 3S. Design a synchronous FSM that performs present state and next state in accordance to the following table.. Present State a b Next State for respective input (XY) b a a a a a b b Output Z a) Derive the minimum excitation and output equations for a full-encoded design using D flip-flops, and show the implementation. b) Derive the minimum excitation and output equations for a one-hot-encoded design using D flip-flops, and show the implementation. Part a): Given X, Y are inputs; two states a & b; output Z. Step - State diagram: Digital Design Logic page 46

7 xy = xy =,, xy =, a / z= b / z= xy =, Step 2. Two states FF for full encoding. Step 3 Assign a unique code for each state: (State variable is Q.) a Q= b Q= Step 4. Create a PS/NS table: (A D FF is required and there is only one Moore-machine output.) PS/NS Table: Input PS X Y Q NS D=Q + Q + D Output Z Q XY Q XY X Y D Q Q z D = X.Q + X Y Q Z=Q Part b): Give X, Y are inputs; two states a & b; output Z. Step - State Diagram xy = xy =,, xy =, a / z= b / z= xy =, Digital Design Logic page 47

8 Step 2. Two states 2 FF for one-hot encoding Step 3 Assign a unique code for each state: (State Variable is Q & Q 2.) a Q Q 2 = b Q Q 2 = Step 4. Create a PS/NS table: (D FFs are required and we only have one Moore-machine output.) PS/NS Table: Input PS X Y Q Q 2 NS Q + + Q 2 D=Q + D D 2 Output Z Note: Invalid states will be directed to Q Q 2 = state with output Z= XY Q Q 2 D = X.Q.Q 2. + X.Y.Q.Q 2 Q Q 2 XY D 2 = D Q Q 2 XY Z= Q.Q 2 Step 5. Schematics X Y D Q Q D 2 Q 2 Q 2 Z Digital Design Logic page 48

9 3U. Design a synchronous FSM that performs present state and next state in accordance to the following table.. Present State (PS) a b Next State for respective input (XY) a b a b a b b a Output Z a) Derive the minimum excitation and output equations for a full-encoded design using T flip-flops, and show the implementation. b) Derive the minimum excitation and output equations for a one-hot-encoded design using T flip-flops, and show the implementation. 4S. Design a synchronous FSM according to the following diagram using rising-edge D flip-flops. Direct any illegal states to state a. States: a b c a b c Y Y 2 RCO Assign a unique code for each state assignment based on two state variables. State Y Y2 a b c Note : Illegal state output is and is directed to state a. Excitation and output equations: PS Y Y 2 NS Y Y 2 D=Y + D D 2 Output RCO D = Y.Y 2 + Y.Y 2 ; D 2 = Y.Y 2 ; RCO = Y + Y 2 Digital Design Logic page 49

10 D Y Y RCO D 2 R Y 2 Y 2 4U. Design a synchronous FSM according to the following diagram using rising-edge D flip-flops. Direct any illegal states to state a. States: a b c a b c Y Y 2 RCO 5S. Design a synchronous circuit using positive-edge-triggered T flip-flops for the following state diagram. a, Y Y 2, Z Z 2 X b, d, c, Digital Design Logic page 5

11 a) Derive the PS/NS table for the machine. b) Derive the minimum excitation and external output equations. c) Draw the circuit schematics. a) PS/NS table with state codes PS X Y Y 2 NS Y + + Y 2 Excitation Input T T 2 Output Z Z 2 b) K-maps XY Y 2 XY Y 2 T T 2 T = X.Y 2 + X.Y T 2 = Y Y 2 + X.Y Z =.Y Z 2 = Y + X Y 2 Z Z 2 c) Schematic Digital Design Logic page 5

12 X T Q Q Z 2 T 2 Q 2 Q 2 Z 5U. Design a circuit (FSM) using JK-ff that performs the function described by the following state: // / Reset // Happy Sad State X/Z // SoSo / 6S. Use D flip-flops to design an automatic room light control that turns the light on only when someone is in the room. Light should be off when no one is in the room. Assume the room capacity is 2. (Door has two sensors, one detecting a person entering in= and one detecting a person leaving out= ). Start with no one in the room. Step System Diagram In(: person in) Out(: person out) Light Control Light (: off, : on) Digital Design Logic page 52

13 Step 2 State Diagram,,,,,,,,,,,,,, State In, Out, Z -Person -Person 2-Person,,,, Step 3 State Assignment State Name Q Q 2 -Person -Person 2-Person Not used Step 4 Excitation and Output Equations In out Q Q 2 + Q + Q 2 Z x x x x x x x x x x x x x x x x Digital Design Logic page 53

14 Q Q 2 Q Q 2 Q Q 2 In Out In Out In Out x x x x x x x x x x x x x x x D =Q + + = in.out.q + in.out.q + in.out.q 2 D 2 =Q = in.out.q 2 + in.out.q + in.q 2 + out. Q 2. Z= Q + Q 2 Step 5 Schematics in out U U U# Description Vcc Gnd N.C. U U2 U3 U4 D Q Q Z D 2 Q 2 Q 2 Engr 25 Design Instructor 9/9/9 6U. Design a locking system with 8 keys ( through 6 and * keys). The system is locked normally and it unlocks only when the valid code sequence *236 has been entered. Entering any other sequence locks the system. Hint: start with a system diagram. 7S. Design a ILCW sequence detector using the classical design technique, full encoding and rising edge D flip flops. ILCW operation is described by the following state diagram when X is the input and Z Z 2 is the 2-bit Digital Design Logic page 54

15 output. Show your work for each of the classical design steps. X X X a / Z Z 2 X X b / Z Z 2 c / Z Z 2 Reset X Step. Organizing design State Diagram (Done) Step 2. 2 #FF # of State # of State = 3 Step 3. Assign unique code/state y y2 State a b c -- Step 4. Select D-ff, draw PS/NS table, Write Excitation equation and output equation Input PS NS Output x y y2 y + y2 + Z Z You could also go to state for the unassigned states You could also go to state for the unassigned states y y 2 x - - D = y + = x.y 2 + x.y y y 2 x - - D 2 = y + 2 = x.y.y 2 + x.y 2 y y 2 x - - Z = y y 2 y y 2 x - - Z 2 = y 2 Digital Design Logic page 55

16 x D y D 2 Y 2 Rst Rst y Rst y 2 Z Z 2 7U. Design a 3-bit gray code counter ( ) using D flip-flop. Digital Design Logic page 56

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