Different encodings generate different circuits

Transcription

1 FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e., for four states, 00, 01, 10, 11 One-hot encoding One state bit per state each state bit stored in one flip-flop. Only one state bit HIGH at once for 4 states, 0001, 0010, 0100, 1000 Requires more flip-flops Often next state and output logic is simpler So fewer gates are required. Chapter 3 <53>

2 Example: one-hot encoding Divide-by-3 counter: output Y is HIGH for one clock cycle out of every 3 cycles. Chapter 3 <54> 54

3 state transition table. output table. state transition with binary encodings state transition with one-hot encodings Chapter 3 <55> 55

4 state transition with binary encodings state transition with one-hot encodings output table. Chapter 3 <56> 56

5 Circuits with binary encoding and one-hot encoding Chapter 3 <57> 57

6 FSM Design Procedure 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. For Moore machine: a. Rewrite state transition table with state encodings b. Write output table 5. For a Mealy machine: Rewrite combined state transition and output table with state encodings 6. Write Boolean equations for next state and output logic 7. Sketch the circuit schematic Chapter 3 <58>

7 Moore vs. Mealy FSM Alyssa P. Hacker has a snail that crawls down a paper tape with 1 s and 0 s on it. The snail smiles whenever the last two digits it has crawled over are 01. Design Moore and Mealy FSMs to compute when the snail should smile. input? a sequence of bits output? smile or not. states? consider both Moore or Mealy Chapter 3 <59>

8 State Transition Diagrams Moore FSM Reset 0 1 S S S2 1 Draw first the success path to find out how many states are needed. Chapter 3 <60>

9 State Transition Diagrams Mealy FSM Reset 0/0 S0 1/0 0/0 S1 1/1 Mealy Digital Design FSM: and Computer arcs Architecture: indicate ARM input/output Edition 2015 Chapter 3 <61>

10 State Transition Diagrams Moore FSM Reset 0 1 S S S2 1 Mealy FSM Reset 0/0 S0 1/0 0/0 S1 1/1 Mealy FSM: arcs indicate input/output Chapter 3 <62>

11 Moore FSM State Transition Table Current State Inputs Next State S 1 S 0 A S' 1 S' State Encoding S0 00 S1 01 S2 10 Moore FSM Reset 0 1 six arcs corresponds to six rows in the state transition table. S S1 0 Chapter 3 <63> 0 1 S2 1

12 Moore FSM State Transition Table Current State Inputs Next State State Encoding S 1 S 0 A S' 1 S' S0 00 S1 01 S S 1 = S 0 A S 0 = A Chapter 3 <64>

13 Moore FSM Output Table Current State Output S 1 S 0 Y Y = S 1 Chapter 3 <65>

14 Mealy FSM State Transition & Output Table Current State Input Next State Output S 0 A S' 0 Y S 0 = A Y = S 0 A State Encoding S0 0 S1 1 Mealy FSM Reset 0/0 S0 1/0 0/0 S1 1/1 Chapter 3 <66>

15 Moore FSM Schematic A CLK S' 1 S 1 Y S' 0 S 0 r Reset S 1 = S 0 A S 0 = A Y = S 1 Chapter 3 <67>

16 Mealy FSM Schematic A CLK S' 0 S 0 Y r Reset S 0 = A Y = S 0 A Chapter 3 <68>

17 Moore & Mealy Timing Diagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11 CLK Reset A S Y S Moore Machine?? S0 S1 S2 S1 S2 S0 S1 S2 S0 Mealy Machine?? S0 S1 S0 S1 S0 S1 S0 Y Chapter 3 <69>

18 More on Flip-Flops Chapter 3 <70> 70

19 SR Latch NOR and NAND implementations S (set) SR latch Q R (reset) Q S=0, R=0, then Q=Q prev S=1, R=1, then Q=0, Q =0 S=1, R=1, then Q=Q prev Active low v.s. active high. They can be used for both implementations. Reset can also be called CLEAR. 71

20 Variations of Flip-Flop (recall homework) JK flip-flop: when JK=11, toggles: 1à0, 0à1 T flip-flop: Toggles on every rising clock edge Equivalent to JK FF with inputs tied together C J K Q next 0 x x No change No change (reset) (set) Q current C T Q next 0 x No change 1 0 No change 1 1 Q current C=1 in the above tables means rising edge. C=0 in the above tables means LOW. 72

21 Characteristic tables & equations D Q(t+1) Operation 0 0 Reset 1 1 Set J K Q(t+1) Operation 0 0 Q(t) No change Reset Set 1 1 Q (t) Complement T Q(t+1) Operation 0 Q(t) No change 1 Q (t) Complement Q(t+1) = D Q(t+1) = K Q(t) + JQ (t) Q(t+1) = T Q(t) + TQ (t) = T Å Q(t) Q(t) current state; Q(t+1) next state. Or sometimes, we use Q for current state; Q + for next state. 73

22 Summary of three FFs X X X X

23 Example, partial state transition table, and its wavedrom code. {signal: [ { name: "Clock", wave: ' ', node: '...'}, {name: 'X', wave: '01...', node: '.a...'}, {name: 'Q_1*', wave: '0...1.', node: '..b.f..'}, {name: 'Q_0*', wave: '0.1.0.', node: '..c.g.'}, {name: 'Q_1', wave: '0...1', node: '...d...'}, {name: 'Q_0', wave: '0..1.0', node: '...e...'}, ], edge: ['a~>b', 'a~>c', 'b~>d', 'c~>e','d~>f', 'e~>g',] } Chapter 3 <75> 75

24 TimingAnalyzer Demo to draw timing diagram Chapter 3 <76> 76

25 More on FSM Design Recall the procedure: 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. For Moore machine: a. Rewrite state transition table with state encodings b. Write output table 5. For a Mealy machine: Rewrite combined state transition and output table with state encodings 6. Write Boolean equations for next state and output logic 7. Sketch the circuit schematic Chapter 3 <77>

26 Example: Chapter 3 <78> 78

27 Chapter 3 <79> 79

28 Example: A snail smiles whenever she slides over the pattern 1101 or the pattern Then, draw a combined state transition and output table with binary encodings Chapter 3 <80> 80

29 Chapter 3 <81> 81

30 Deriving the state transition diagram from a schematic A reverse process of FSM design. q Examine circuit, stating inputs, outputs, and state bits. q Write next state and output equations. q Create next state and output tables. q Reduce the next state table to eliminate unreachable states. q Assign each valid state bit combination a name. q Rewrite next state and output tables with state names. q Draw state transition diagram. q State Digital Design in words and Computer what Architecture: the ARM FSM Edition does Chapter 3 <82> 82

31 The input is A 1:0 and the output is Unlock. The state bits are already labeled. This is a Moore machine because the output depends only on the state bits. Write down the next state and output equations directly: Chapter 3 <83> 83

32 writes down the next state and output tables from the equations. Chapter 3 <84> 84

33 Remove unused states and combine rows using don t cares. The S 1:0 = 11 state is never listed as a possible next state, so rows with this current state are removed. For current state S 1:0 = 10, the next state is always S 1:0 = 00, independent of the inputs, so don t cares are inserted for the inputs. Assign names to each state bit combination: S0 is S 1:0 = 00, S1 is S 1:0 = 01, and S2 is S 1:0 = 10. Chapter 3 <85> 85

34 Chapter 3 <86> 86

35 More Examples Problem 1. Analyze the following FSM. Write down the state transition and output tables, and sketch the state transition diagram. The output is Y. You should use binary state encoding, and list all possible states in your state transition table and diagram. Then, you should remove redundant states, and derive a simplified state table and diagram. 87

36 Problem 2. Output Y Analyze the following FSM that consists of two T flip flops and two AND gates. Write down the state transition and output tables, and sketch the state transition diagram. Note that this problem uses a T flip-flop instead of a D flip-flop in the FSM. 88

37 Problem 3. Design an FSM with one input A and one output Y. Y should be 1 if A has been 1 during at least three most recent consecutive clock cycles. Show your state transition diagram, encoded state transition table (you should use binary encoding), and the next state and output Boolean equations if you use D flip-flops in your FSM (as we usually do in Chapter 3 of the textbook). Problem 4. Redo the previous problem assume that you use J-K flip-flops in your FSM, instead of D flip-flops. Note that if you need two J-K flip-flops A and B, then you need to write down Boolean equations for J A, K A, J B, and K B. 89

38 Exercise Analyze the FSM shown below. Write the state transition and output tables and sketch the state transition diagram. Describe in words what the FSM does. 2-<90>

39 Textbook exercise <91>

40 Problem. Provide the Q output signal using a J-K flip-flop, which has an active low Set and an active low Reset and they are asynchronous. The asynchronous inputs take precedence over the synchronous inputs. Assume that propagation delays are negligent Chapter 3 <92> 92

41 Factoring State Machines Break a complex FSM into smaller interacting FSMs outputs of some machines are the inputs of some other machines Example: Modify traffic light controller to have Parade Mode. Two more inputs: P, R When assert P, i.e., P = 1, for at least one cycle, enter Parade Mode & Bravado Blvd light stays green. Once put into parade mode, controller proceeds through its usual sequence till L B turns green, then remains in that state with L B green until parade mode ends. When asserting R, i.e., R = 1, for at least one cycle, leave Parade Mode. Chapter 3 <93>

42 Parade FSM Step 1: Unfactored FSM P R T A T B Controller FSM L A L B Step 2: Factored FSM P R Mode FSM M Mode FSM asserts M when in parade mode. T A T B Lights FSM L A L B Controller FSM Chapter 3 <94>

43 Factored FSM Reset S0 L A : green L B : red T A TA S1 L A : yellow L B : red S3 L A : red L B : yellow MT B S2 L A : red L B : green Reset S0 M: 0 P P R S1 M: 1 M + T B R Lights FSM Mode FSM Chapter 3 <95>

44 Unfactored FSM S0, S1, S2, S3 handle normal mode. S4, S5, S6, S7 handle parade mode. Chapter 3 <96>

45 Compare Reset T A TA S0 L A : green L B : red S1 L A : yellow L B : red S3 L A : red L B : yellow MT B S2 L A : red L B : green Reset S0 M: 0 P P R S1 M: 1 M + T B Lights FSM Mode FSM R Reset T A TA S0 L A : green L B : red S1 L A : yellow L B : red original FSM S3 L A : red L B : yellow S2 L A : red L B : green T B Chapter 3 <97> T B