CSE 140: Components and Design Techniques for Digital Systems. Lecture 9: Sequential Networks: Implementation

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1 CSE 4: Components and Design Techniques for Digital Systems Lecture 9: Sequential Networks: Implementation CK Cheng Dept. of Computer Science and Engineering University of California, San Diego

2 Implementation Format and Tool Mealy & Moore Machines, Excitation Table Procedure State Table to Logic Diagram Excitation Tables FFs Examples 2

3 Canonical Form: Mealy and Moore Machines Mealy Machine: y i (t) = f i (X(t), S(t)) Moore Machine: y i (t) = f i (S(t)) s i (t+) = g i (X(t), S(t)) x(t) C C2 y(t) x(t) C C2 y(t) CLK S(t) CLK S(t) Mealy Machine Moore Machine 3

4 iclicker In the logic diagram below, a D flip-flop has input x and output y. A: x=, y= B: x=q(t+), y= C: x=, y=q(t+) x y D: None of the above D Q CLK 4

5 Understanding Current State and Next State in a sequential circuit Yesterday is gone. Tomorrow has not yet come. We have only today. Let us begin. Mother Teresa sunrise today 5

6 Implementation Format Canonical Form: Mealy & Moore machines State Table Netlist Tool: Excitation Table x(t) C C2 y(t) CLK Q(t+) = g(x(t), ) Circuit C y(t) = f(x(t), ) Circuit C2 6

7 Implementation Tool: Excitation Table Example: State Table x(t) id x(t) Q(t+) 2 3 C CLK Find D, T, (S R), (J K) to drive F-Fs 7

8 Implementation Tool: Excitation Table Example: State Table id x(t) Q(t+) 2 3 x(t) C T(t) Example with T flip flop CLK Excitation Table id x(t) T(t) Q(t+) 2 3 8

9 Implementation Tool: Excitation Table Implement combinational logic C D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,) Example: x(t) C CLK Excitation Table id x(t) T(t) Q(t+) 2 3 9

10 Implementation: Procedure State Table => Excitation Table Problem: To implement C, we need D(t), T(t), (S(t) R(t)), (J(t) K(t)) as functions of (x,).. From state table, we have NS: Q(t+) = g(x(t),) 2. Excitation Table of F-Fs: The setting of D(t), T(t), (S(t) R(t)), (J(t) K(t)) to drive to Q(t+). 3. Combining and 2, we have excitation table of C: D(t), T(t), (S(t) R(t)), (J(t) K(t)) = h(x,).

11 Implementation: Procedure F-F State Table <=> F-F Excitation Table PS PS DTSRJK NS Q(t+) NS Q(t+) DTSRJK D F-F D(t)= e D (Q(t+), ) T F-F T(t)= e T (Q(t+), ) SR F-F S(t)= e S (Q(t+), ) R(t)= e R (Q(t+), ) JK F-F J(t)= e J (Q(t+), ) K(t)= e K (Q(t+), )

12 Excitation Table State table of JK F-F: Excitation table of JK F-F: NS PS JK Q(t+) JK Q(t+) Ex: If is, and Q(t+) is, then JK needs to be -. 2

13 Excitation Tables and State Tables Excitation Tables: State Tables: PS NS Q(t+) JK JK SR PS NS - XY - SR SR PS iclicker A. XY= - B. XY= C. XY= D. XY= - E. None of the above Q(t+) Q(t+) - - Q(t+) 3

14 Excitation Tables and State Tables Excitation Tables: State Tables: T PS NS Q(t+) T PS T Q(t+) D PS NS Q(t+) D PS D Q(t+) 4

15 Implementation: Procedure. State table: y(t)= f(, x(t)), Q(t+)= g(x(t),) 2. Excitation table of F-Fs: D(t)= e D (Q(t+), ); T(t)= e T (Q(t+), ); (S, R), or (J, K) 3. From & 2, we derive excitation table of the system D(t)= h D (x(t),)= e D (g(x(t),),); T(t)= h T (x(t),)= e T (g(x(t),),); (S, R) or (J, K). 4. Use K-map to derive combinational logic implementation. D(t)= h D (x(t),) T(t)= h T (x(t),) y(t)= f(x(t),) 5

16 Implementation: Example Implement a JK F-F with a T F-F J K C T Q Q Q Implement a JK F-F: JK Q(t+) = h(j(t),k(t),) = J(t)Q (t)+k (t) PS JK 6

17 Example: Implement a JK flip-flop using a T flip-flop id Excitation Table of T Flip-Flop PS NS J(t) Q(t+) Excitation Table of the Design K(t) Q(t+) T(t) T(t) = XOR ( J(t)Q (t) + K (t)) i.e. Q(t+)(t) = JQ (t)+k. State table: y(t)= f(, x(t)), Q(t+)= g(x(t),) 2. Excitation table of F-Fs: D(t)= e D (Q(t+), ); T(t)= e T (Q(t+), ); (S, R), or (J, K) 3. From & 2, we derive excitation table of the system D(t)= h D (x(t),)= e D (g(x(t),),); T(t)= h T (x(t),)= e T (g(x(t),),); (S, R) or (J, K). 4. Use K-map to derive combinational logic implementation. D(t)= h D (x(t),) T(t)= h T (x(t),) y(t)= f(x(t),) 7

18 Example: Implement a JK flip-flop using a T flip-flop T(J,K,Q): K J T = K(t) + J(t)Q (t) J K T Q Q 8

19 iclicker Before state assignment, the relation of its state table and excitation table is A.One to one B.One to many C.Many to one D.Many to many E.None of the above 9

20 Let s implement our free running 2-bit counter using T-flip flops S S 3 S S 2 State Table PS Next state S S S 2 S 3 S S 2 S 3 S 2

21 Let s implement our free running 2-bit counter using T-flip flops S S 3 S State Table S 2 State Table with Assigned Encoding Current Next S S S 2 S 3 S S 2 S 3 S 2

22 Let s implement our free running 2-bit counter using T-flip flops Excitation table id Q (t) Q (t) T (t) T (t) Q (t+) Q (t+)

23 Let s implement our free running 2-bit counter using T-flip flops Excitation table id Q (t) Q (t) T (t) T (t) Q (t+) Q (t+)

24 Let s implement our free running 2-bit counter using T-flip flops Excitation table id Q (t) Q (t) T (t) T (t) Q (t+) Q (t+) 2 3 T (t) = T (t) = Q (t+) = T (t) Q (t)+t (t)q (t) Q (t+) = T (t) Q (t)+t (t)q (t) 24

25 Let s implement our free running 2-bit counter using T-flip flops Excitation table id Q (t) Q (t) T (t) T (t) Q (t+) Q (t+) 2 3 T (t) = T (t) = Q (t) 25

26 Free running counter with T flip flops T Q Q Q T T Q Q Q T (t) = T (t) = Q (t) 26

27 Summary: Implementation Set up canonical form Mealy or Moore machine Identify the next states state diagram state table state assignment Derive excitation table Inputs of flip flops Design the combinational logic don t care set utilization 27

Lecture 8: Sequential Networks and Finite State Machines

Lecture 8: Sequential Networks and Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Spring 2014 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University