Digital Logic Design - Chapter 4

Size: px

Start display at page:

Download "Digital Logic Design - Chapter 4"

Kimberly Wheeler
5 years ago
Views:

1 Digital Logic Design - Chapter 4 1. Analyze the latch circuit shown below by obtaining timing diagram for the circuit; include propagation delays. Y This circuit has two external input and one feedback input, therefore has total of 8 possible input conditions: Input Output Current Y Next Y Corresponding Timing Diagram: Y 1U. Analyze the latch circuit shown below by obtaining timing diagram for the circuit; include propagation delays. Y 2. Analyze the Flip-Flop circuit using K-map to determine if the input conditions =11 transition to =00 with initial state =0 can result in a critical race. Digital Design Logic page 31

2 = 110 are changed simultaneously to 00 may change first = = 0 table state next changes, = = 0 table state may change first = = 1 (unstable state). Next changes, = = 1 (stable state) Note: Depending on if changed first or changed first, the final state will be different; therefore, we have a critical race. 2U. Analyze the Flip-Flop circuit using K-map to determine if the input conditions =00 transition to =11 with initial state =1 can result in a critical race. 3. Draw a clock signal with four 1-to-0 timing events, a nonzero setup time, t su, and a nonzero hold time, t h. Also draw one excitation input signal EI that follows the sequence 0101 and meets the setup and hold time requirements. In the excitation input, the first bit in the sequence (0) occurs in time for the first clock timing event, the second bit in the sequence (1) occurs in time for the second clock timing event, and so forth. #1 #2 #3 #4 EI 3U. Draw a clock signal with five 0-to-1 timing events, a nonzero setup time, t su, and a nonzero hold time, t h. Also draw one excitation input signal EI that follows the sequence and meets the setup and hold time requirements. In the excitation input, the first bit in the sequence (1) occurs in time for the first clock timing event, the second bit in the sequence (0) occurs in time for the second clock timing event, and so forth. Digital Design Logic page 32

3 4. how how a positive-edge-triggered D flip-flop and an inverter can be used as a negative-edge D flip-flop. D D FF D FF 4U. how how a positive-edge-triggered D flip-flop and other logic gates can be used to design a positive-edge T flip-flop. 5. Complete the timing diagram shown below for a negative-edge-triggered J-K flip-flop. Assume that the J and K inputs always meet the setup and hold time requirements for the J-K flip-flop. Hint: Use the JK flip-flop characteristic table. J J K K Digital Design Logic page 33

4 J J K K 5U. Complete the timing diagram shown below for a negative-edge-triggered flip-flop. Assume that the and inputs always meet the setup and hold time requirements for the flip-flop. Hint: Use the flip-flop characteristic table Obtain the state diagram for the circuit shown below. D1 1 Y1 ystem Clock CL D2 2 Y2 Case 1 tate Diagram (when CL = 0): Digital Design Logic page 34

5 00 eset 2 1 Case 2. tate Diagram (when CL = 1): 1 + = D 1 = = D 2 = 1 P/N Table CL 11 6U. Obtain the state diagram for the circuit shown below. x D1 1 Y1 z ystem Clock D2 2 Y2 7. Analyze the state machine shown below to obtain the following items: a) Excitation input and external output equations b) P/N c) tate Diagram Digital Design Logic page 35

6 Z2 X J1 Y1 Z1 K1 Y1 J2 Y2 K2 Y2 Y a) Excitation Equations: J1= X K1 = X.Y2 + X.Y2 J2 = Y1 K2 = X + Y1 Apply the excitation equations into the JK ff Characteristic equation (Yi + =Ji.Yi + Ki.Yi) Y1 + = X.Y1 + (X.Y2 + X.Y2) Y1 Y2 + = Y1.Y2 + (X + Y1).Y2 External Outputs Z 1 = Y 1.Y 2 Z 2 = Y 1.Y 2 + X b) P/N Table y 2 y 1 x y 2 + y 1 + J 1 K 1 J 2 K 2 Z 1 Z Digital Design Logic page 36

7 c) tate Diagram 0/1 x/ Z 2 0/1 00/0 1/0 1/0 1/1 01/0 0/1 1/0 y 2 y 1 /Z 1 11/1 0/1 10/0 7U. Analyze the state machine shown below to obtain the following items: a) Excitation input and external output equations b) P/N c) tate Diagram Z 2 X Y1 Z 1 Y1 Y2 Y2 Y 8. Obtain the state diagram for the circuit shown below. What is the mod of the counter? Is this counter useful? Change only the value being loaded at the inputs to obtain a mod 9 counter. What value must be loaded to do this? Digital Design Logic page 37

8 Vcc Binary UP Counter CL LOAD CO CL and LOAD are synchronous inputs CL will set all output to 0 LOAD allows values on A,B,C and D got to A, B, C and D. D is MB & A is LB Y A B C D A B C D GND 0011 Preload Counter is a mod-6 counter ( ). It can be used to count from 3 to 8. If A,B,C and D were grounded, then the counter would count from 0 to 8 (mod-9). 8U. Obtain the state diagram for the circuit shown below. What is the mod of the counter? Is this counter useful? Change only the value being loaded at the inputs to obtain a mod 9 counter. What value must be loaded to do this? Digital Design Logic page 38

9 Vcc Binary UP Counter CL LOAD CO CL and LOAD are synchronous inputs CL =0 will set all output to 0 LOAD=1 allows values on A,B,C and D to pass through to A, B, C and D. D is MB & A is LB Y A B C D A B C D GND 9. What is the frequency of the fastest clock for a circuit using D flip flops with t hold =5 nsec. and t setup = 10 nsec. Assuming there are no other limitations. Tclk > 15 nsec. fclk < 10 9 /15 or Mhz 9U. What is the frequency of the fastest clock for a circuit using D flip flops with t hold =50 psec. and t setup = 150 psec. Assuming there are no other limitations. Digital Design Logic page 39

10 10U. Analyze the following logic circuit: x T 0 0 Y 0 T 1 1 Y 1 Z 1 0 Y 0 1 Y 1 Y Z 2 11U. Analyze the following logic circuit: x J 0 0 Y 0 J 1 1 Y 1 Z K 0 0 Y 0 K 1 1 Y 1 Y Digital Design Logic page 40

6 Synchronous State Machine Design

6 Synchronous State Machine Design Design of synchronous counters. Based on the description of the problem, determine the required number n of the FFs - the smallest value of n is such that the number of states N 2 n and the desired counting