Sequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science
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1 Sequential Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design
2 Sequential Logic Combinational circuits with memory elements called sequential logic. Block diagram of the sequential logic is, 2
3 Sequential Logic Sequential circuit consists of combinational logic circuit to which memory elements are connected to form a feedback path. Memory elements are devices capable of storing binary information within them. The binary information stored in the memory elements at any given time defines the state of the sequential circuits. For example, ALU Operation, MUX and DeMUX, The Counter Circuits etc 3
4 Latches and Flip Flops A latch is a temporary storage device that has two stable states. Its output can be changed by applying appropriate inputs. A latch normally has two inputs, and two outputs Q and Q. The Latch is said to be in Logic High when, Q=1 and Q =0 And vice versa. 4
5 Flip Flops A Latch is memory element which is able to retain the information stored in it. Flip flop circuit can be constructed from two NAND or NOR Gates. The cross coupled connection constitute a feedback. Such type of circuits are also called direct coupled RS flip flop or SR latch. 5
6 Basic Flip Flop Circuit The figure describes the circuit as follow, 6
7 Basic Flip Flop Circuit To analyze the operation of the circuits on previous slide, We know that the output of the NOR gate is 0 if any input is one, and vice versa. Starting for the draw run take all the possibilities, Set=1 and Reset=0 then Q=1 and Q =0 Set=0 and Reset=0 then Q=1 and Q =0 Memory Set=0 and Reset=1 then Q=0 and Q =1 Set=0 and Reset=0 then Q=0 and Q =1 Memory Set=1 and Reset=1 then Q=0 and Q =0 (Indeterminate state) 7
8 Flip Flop with NAND Gates For S=1, R=1, Q=0, Q =1 after S=1, R=0 Memory For S=1, R=1, Q=1, Q =0 after S=0, R=1 Memory 8
9 RS-Flip Flop The operation of the basic flip flop can be modified by providing an additional control input that determines when the state of the circuit is to be changed. An RS flip flop with a clock pulse(cp) is shown. It consists of basic flip flop circuit and two additional NAND gates. CP acts as an enable signal input. 9
10 RS-Flip Flop Q S R Q(t+1) Invalid invalid 10
11 D-Flip Flop One way to eliminate the undesirable condition of the indeterminate state in the RS flip flop is to ensure that inputs S and R are never Equal to 1 at the same time. It has only two inputs D and CP. The D input directly goes to the S input and its complement is applied to R input. As long as the pulse input is at 0, the outputs of the gates 3 and 4 are at the one level and the circuit cannot change state regardless of the value of D. 11
12 If D=1, D-Flip Flop Q output goes to 1, placing the circuit in the set state. If D=0, Output Q goes to 0, and circuit switches to the clear state. 12
13 D-Flip Flop 13
14 JK-Flip Flop A JK flip flop is a refinement of the RS flip flop to over come the indeterminate states. Input J and K behave like inputs S and R to Set and Clear the flip flop. J for Set and K for Reset. A JK flip flop is constructed with two cross coupled NOR gates and two AND gates. Output Q is ANDed with K and CP inputs so that the FF is cleared during a CP only if Q was previously 1. 14
15 JK-Flip Flop Output Q is ANDed with J and CP inputs so that FF is set with a CP only when Q was previously 1. Q J K Q(t+1) Characteristic Table 15
16 JK-Flip Flop 16
17 It s a single input version of JK flip flop. T-Flip Flop The destination T comes from the ability of the FF to toggle, or complement its state. The characteristic table and equation show that when T=0, Q(t+1)=Q, that is, the next state is the same as the present state and no change occurs. When T=1, then Q(t+1)=Q and the state of the FF is complemented. 17
18 T-Flip Flop 18
19 Master Slave Flip Flop A Master Slave FF is constructed from two separate FF. One circuit serves as a master and other as a slave, and the overall circuit is called to as a Master Slave Flip Flop. 19
20 20
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