Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

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1 Serial : 5SP_CS_W_Digital Logic_598 Delhi Noida hopal Hyderabad Jaipur Lucknow Indore Pune hubaneswar Kolkata Patna Web: info@madeeasy.in Ph: CLSS TEST 289 COMPUTER SCIENCE & IT Subject : Digital Logic Date of test : 5/9/28 nswer Key. (b) 7. (b) 3. (a) 9. (c) 25. (b) 2. (b) 8. (b) 4. (b) 2. (d) 26. (c) 3. (b) 9. (b) 5. (c) 2. (d) 27. (a) 4. (d). (b) 6. (b) 22. (c) 28. (c) 5. (c). (a) 7. (c) 23. (c) 29. (c) 6. (a) 2. (d) 8. (b) 24. (a) 3. (c)

2 CT28 CS Digital Logic 7 Detailed Explanations. (b) Overall MOD = = 6 Lowest frequency is output frequency 2. (b) f out = = 4 khz (54) (4) b b = (3) b or (54) b = (4) b (3) b The expression in decimal number system is (5 b + 4 b ) = (4 b ) ( b + 3 b ) 5b + 4 = 4 (b + 3) b = 2 4 = 8 3. (b) It is a toggle flipflop, the values toggle Q : initial state 4. (d) Excitation table Qn Qn+ J K X X X X 5. (c) Using POS form Z = ( + + C)( + + C) = ( + )( + ) + C = + C = C + ( ) 6. (a) + = ( + ) = + = ( + ) = (+ ) = ( + ) = Thus for F = = ; = and =

3 8 Computer Science & IT 7. (b) 8. (b) x y x y = ( xy + xy) xy = ( xy xy) + ( xy xy) = y( x x) + x( y y) = y + x Y = I SS + I SS + I 2 SS + I 3 SS Y = + () = + = + 9. (b) Essential prime implicant is a prime implicant which is having atleast one minterm which is not the part of any other prime implicant. Using Kmap for the given function we get CD Here total number of prime implicants = 6 and the number of essential prime implicants = 2. (b) S S C Q C C Q = C + C + C + C + C + C + C = Σm (, 2, 3, 4, 5, 6, 7) = ΠM(). (a) 422 code is a self complementing code = 9 For a self complementing code system, codeword of 5 = s complement of codeword of 4 5 = 9 4 i.e, 9 s complement of 4. so, codeword of 5 = s complement of () = 2. (d)

4 CT28 CS Digital Logic 9 3. (a) > is possible when either of the following conditions is satisfied. When > i.e., when G = 2. When ( = ) and ( > ) i.e., when E G = So, the oolean expression for G is G = E G + G X Y Z YZ X I I I 2 I 3 Thus solution is option (a). X X 4. (b) T min = minimum clock period required = time delay from the time of active clock edge to the point of time, where the latest change appears at the input of flipflops before the application of next active clock edge. Let us assume active clock edge is applied at t =, then, the latest change in Q appears at t = 5 µs the latest change in Q appears at t = 4 µs the latest change in Q 2 appears at t = 3 µs the latest change in D 2 appears at t = 4 µs the latest change in D appears at t = 8 µs the latest change in D appears at t = µs so T min = µsec f c max = = = khz T µ sec min 5. (c) Given circuit is of 8 to multiplexer. Multiplexer is used to select any one input out of all inputs at a time. Hence, output will be equal to I 5 for a particular combination of selection lines. For D = ; C = ; = combination selects the I 5. lso, we have the given logic function as F = C + D + CD + CD

5 Computer Science & IT So, by substituting D =, C =, and =, We get, F = F = Thus, input to I 5 must be equal to. 6. (b) Given that, T carry = 5 ns and T sum = ns a 2 b 2 a b a b c (initial carry) F.. 2 F.. F.. Final carry c 3 s 2 c 2 s c s From the above circuit we have, T s = ns T s = ( ns + 5 ns) = 5 ns T s 2 = ( ns + ns) = 2 ns Here, we see the final (sum) result will take T = 2 ns maximum rate of addition/sec = 9 T = 2ns = 2 =.5 8 = (c) The output z is connected from inverted outputs of the FFs through ND gate, i.e. z = QQQC = Q + Q + QC Hence, the output z will be high only when all FF s output are zero, i.e. Q = Q = Q C = Let initially z =, then we obtain the truth table for the circuit as CLK number initial Present State Inputs Next State J K J K J + + Q Q Q C C K C Q Q z Q C + It is MOD6 counter. So, output z will be after 6 clock pulses.

6 CT28 CS Digital Logic 8. (b) When Q 4 Q 3 is, then CLR =, hence the count goes back to. 9. (c) 2. (d) Q 4 Q3 Q2 Q Q Q 4 Q3 Q2 Q Q Q 4 Q3 Q2 Q Q Thus, counter counts 23, and clears at 24. It s a MOD24 counter. f max = ; nt pd t pd = propagation delay of each flipflop and n = number of flip flops t pd = n = sec sec = nsec 4 25 Clk No. Q Q initial It s a Johnson counter after 4 clock pulses the state (Q Q ) will be () again. 2. (d) The truth table for function f(,, C) is [inverter is on when majority of connection fails] C f The Kmap for f(,, C) is C f(,, C) = + C + C

7 2 Computer Science & IT 22. (c) J K Q Qn Q n + = + + Qn Q n + = + Q n = + Qn n+ 23. (c) Output of the 4 : MUX circuit in Figure is Y = I + I + I 2 + I 3 Output of the circuit in Figure is Y = C = C + C + C + C On comparison I = C I = C I 2 = C = C 24. (a) Using Truth table: I 3 C D S S2 = 2 = 2 2 = 2 3 = 2 = 2 = 2 2 = = 3 > 2 2 = 2 2 = = 4 > = 6 > 2 3 = 2 3 = 3 > = 6 > = 9 > 2 F CD F = F = + C + CD + D + C

8 CT28 CS Digital Logic (b) The kmap has to rearranged as C CD D C F = C + D + C 26. (c) 27. (a) In the circuit, we have S = C = S = ( ) = ( ) + ( ) = + + = + C = ( )( ) = ( + ) = D = QQ 2 = Q+ Q2 D = Q D 2 = Q The truth table for the circuit is obtained below. CLK number initial Present State Q 2 Q Q Inputs D 2 D D Q 2 + Next State Q + Q fter 4 clock pulses, output is Q 2 Q Q = 28. (c) Redrawing the digital circuit 2 2 Y From the figure we get, Y = 2 2 So, Y is XOR of six boolean variables and Y will be when odd number of variable are. Thus there will 6 2 be = 32 cases for the output to be. 2

9 4 Computer Science & IT 29. (c) + + Q Q J K J K Q Q MOD = 3 3. (c) Truth table for output F (X,Y,Z) is shown below Here, X Y Z F F (X, Y, Z) = XYZ + XYZ + XYZ + XYZ = YZ( X + X) + XZ( Y + Y) + XY ( Z + Z) = YZ + XZ + XY Hence, there are total three no. of product terms in the irredundant form of F.

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph: Serial : S_CS_C_Digital Logic_588 Delhi Noida hopal Hyderabad Jaipur Lucknow Indore Pune hubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: -56 CLASS TEST 8-9 COMPUTER SCIENCE & IT Subject : Digital