Vidyalankar S.E. Sem. III [EXTC] Digital Electronics Prelim Question Paper Solution ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD = B

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1 . (a). (b). (c) S.E. Sem. III [EXTC] igital Electronics Prelim Question Paper Solution ABC ABC ABC ABC ABC ABC ABC ABC = B LHS = ABC ABC ABC ABC ABC ABC ABC ABC But ( ) = = ABC( ) ABC( ) ABC( ) ABC( ) LHS = ABC ABC ABC ABC = AB(C C) AB(C C) = AB AB ( (C C) = ) = B(A A) = B ( (A A) = ) LHS = RHS Hence proved HEX to ecimal : (BC AC) 6 = = HEX to Binary : (BC AC) 6 B = () 2 C = () 2 A = () 2 = () 2 (BC AC) 6 = ( ) 2 Hex to Octal : (BC AC) 6 = ( ) (BC AC) 6 = ( ) 8 3/Engg/SE/Pre Pap/23/EXTC/E_Soln

2 : S.E. E. (d) 2. (a) Transmitted Bit ata Bit Parity Bit Group Group 2 Group 3 Group 2 and Group 3 are the error combinations, while Group is the correct combination. Bit 3 is common to Group 2 and 3, hence the error bit is 3. Therefore the correct word is (). Master Slave JK Flip Flop 2 3/Engg/SE/Pre Pap/23/EXTC/E_Soln

3 Prelim Question Paper Solution Master is positive level triggered. But due to the presence of the inverter in the clock line, the slave will respond to the negative level. Hence when the clock = I (positive level) the master is active and the slave is inactive, whereas when clock = (low level) the slave is active and the master is inactive. Case I : Clock = X, J = K = (i) For clock =, the master is active, slave inactive. As J = K =. Therefore, output of master, i.e., Q and Q will not change. Hence the S and R inputs to the slave will remain unchanged. (ii) As soon as clock =, the slave becomes active and master is inactive. But since the S and R inputs have not changed, the slave outputs will also remain unchanged. The outputs won't change if J = K =. Case II : Clock =, J = K =. This condition has been already discussed in case f. Case III : Clock =, J = and K =. Clock = : Master active, slave inactive. Therefore, outputs of the master become Q = and Q =. That means S = and R =. Clock = : Slave active, master inactive. Therefore, outputs of the slave become Q = and Q =. Again if clock = : Master active, slave inactive. Therefore, even with the changed outputs Q = and Q = feedback to master, its outputs will Q = and Q =. That means S = and R =. Hence with clock = and slave becoming active, the outputs of slave will remain Q = and Q =. Thus we get a stable output from the Master Slave. Case IV : Clock =, J =, K =. Clock = : Master active, slave inactive. Therefore, outputs of master become Q = and Q =, i.e., S =, R =. Clock = : Master inactive, slave active. Therefore, outputs of slave become Q = and Q =. Again if clock = then it can be shown that the outputs of the slave are stabilized to Q = and Q =. Case V : Clock =, J =, K =. Clock = : Master active, slave inactive. Therefore, outputs of master will toggle. So S and R also will be inverted. Clock = : Master inactive, slave active. Therefore, outputs of the slave will toggle. These changed output are returned back to the master inputs. But since clock =, the master is still inactive. So it does not respond to these changed outputs. This avoids the multiple toggling which leads to the race around condition. Thus the master slave flip flop will avoid the race around condition. 3/Engg/SE/Pre Pap/23/EXTC/E_Soln 3

4 : S.E. E 2. (b) Using 8 : y = m (,, 2, 3, 8, 9, 3, 4) A B C Y 2. Using 4 : multiplexer : A B C Y A B C Y AB = Y =? C Y = AB = Y =? C Y = C Logic Logic AB = Y =? C Y = AB = Y =? C : A B C (MSB) Y C C Y C y 4 3/Engg/SE/Pre Pap/23/EXTC/E_Soln

5 Prelim Question Paper Solution 3. (a) A B Y C C C. Firstly we have to prepare a table where we have binary (4 bitts, B 3 B 2 B B ) inputs and gray (4 bits G 3 G 2 G G ) outputs 2. Truth table is, Logic Logic : 3. Now the next step is very simple. You draw K maps for G 3, G 2, G and G separately. A B y 3/Engg/SE/Pre Pap/23/EXTC/E_Soln 5

6 : S.E. E 4. K maps : 5. Circuit : 6 3/Engg/SE/Pre Pap/23/EXTC/E_Soln

7 3. (b) 4. (a) Characteristic equation of Flip-flop Qn+ = * Q * = Q * = = Q + Q 2 [Q * represents the next state] Q 2 * = 2 = X. Q 2 Prelim Question Paper Solution Z = Q + Q 2 Previous Next State Next State State (x = ) (x= ) Output Q Q 2 Q *+ Q 2 *+ Q *+ Q 2 *+ X= X= Replacing the above states with A =, B =, C =, = Previous Next State Output State X = X = X = X = A C B C C C A B C C Circuit diagram : A B V B R B V BC Q Q 2 V B2 V BE2 A B Y = AB V x V CC R C2 R E2 A B V B4 V BE4 V BE3 Multi emitter i/p stage I C3 R C3 Q 4 Q 3 V o/p A,, C Phase Splitter B Totem pole o/p stage Y = AB 3/Engg/SE/Pre Pap/23/EXTC/E_Soln 7

8 : S.E. E Operation : Case I : A =, B = For this case Q works in normal mode and transistors Q 2 and Q 3 both will be OFF and voltage at V x point will be V CC and this is sufficient to turn ON Q 4 and (because to turn ON Q 4 and voltage V x = V B4 = V BE4 + V = =.4 V) so Q 4 and both will be ON when output V. V = V x V BE4 V = V CC V BE4 V = = 3.6 V = logic V = logic Case II : A =, B = Case III : A =, B = Case IV : A =, B = For this case, transistor Q works in inverse mode due to this Q 2 and Q 3 both will be ON and voltage at V x = V CE2 + V CE2 (sat) + V BE3 = =.9 V This voltage is not sufficient to turn ON Q 4 and because it is less than.4 V. So Q 4 and both will be OFF and output V = V CE3 (sat) =.2 V = logic. Transfer Characteristics of TTL NAN gate : Transfer characteristics gives relationship between input given and output appeared. It shows valid region for operating TTL gate. (i) V I < V a : If V I at one or more of the input is less than V a, then Q works in normal mode and transistor Q 2 and Q 3 both will be turn off and voltage at V x = V CC due to this transistor Q 4 and diode is conduct and output V will be V o = V CC V BE4 (ON) V = V o = 3.6 V = logic logic V OH = 3.6 V logic V OL.2 V V V same as case (I) a V a.7 V V IL slope =.4 b slope = 6.2 c (ii) V I > V C : When V I of all inputs is greater than V C, transistor Q 2 and Q 3 conduct because Q works in inverse mode and voltage at V x =.9 V. This is not V b V c.4 V V IH V IN 8 3/Engg/SE/Pre Pap/23/EXTC/E_Soln

9 Prelim Question Paper Solution sufficient to turn on Q 4 and, so both will be off and output V o = V CE3 (sat) =.2 V = logic (iii) V a < V I < V C : This range is the transition range where translation occurs from a logic to logic output. Assume that all inputs are tied together and V I is increased from, then Q base current is gradually diverted from the emitter of Q to the collector of Q due to this Q 2 will be conduct. This conduction occurs at V I.7 V. i.e. point a on characteristics Q 2 is now operating in active region with a gain. From input to collector determined by the ratio R E2 / R C2. Since Q 4 remains ON, the output follows the gain characteristics of Q 2 and therefore decreases at a slope of.6 [point a to b on transfer characteristics]. At point b, the input is high enough to cause Q 3 to conduct this conduction effectively reduces the emitter impedance of Q 2 and hence increases the gain. So will get steep slope region between points b and c. Q 4 turns OFF at point c and output is at logic state. Parameters : (i) Propagation delay = tp t HL PLH 2 = nsec. (ii) Power dissipation = mw (iii) Fanout : This is the number of similar gates which can be driven by a gate. Fanout = min IOH IOL 4 6, = min IH I, L 4.6 = min (, ) = (iv) Noise Margin High state noise margin NM H = V H V H = =.4 V Low state noise margin NM L = V L V L =.8.4 =.4 V 3/Engg/SE/Pre Pap/23/EXTC/E_Soln 9

10 : S.E. E 4. (b) 3 bit synchronous up counter using T flip flop. +V CC Clk Clk Y Y 2 Y 3 T J K PR FF CLR Y Y T J K Truth table of Mod 8 synchronous counter Count Y 3 Y 2 Y () In mod 8 counter, 3 T flip flops are used. The waveforms for natural count sequence are shown. (2) The T flip flop responds to a negative transition at the clock input and toggles when J and K are high. (3) Flip flop changes state with each negative transition at the clock input. (4) The output of AN gate and goes high whenever the clock is high and FF is high. Therefore, flip flop 2 changes state every alternate clock pulse. (5) The output of AN gate 2 goes high each time the clock is high and both FF and FF 2 are high. The flip flop 3 toggles whenever its clock input (output of AN gate 2) changes from to. (6) Therefore flip flop 3 changes state with every fourth clock pulse. (7) Thus, the synchronous counter provides 8 states. (8) When 8 th clock pulse is applied all flip flops reset. (9) Any synchronous counter can be designed by using particular number of flip flops. PR FF 2 CLR Y 2 Y T J K PR FF 3 CLR Y 3 Y 3/Engg/SE/Pre Pap/23/EXTC/E_Soln

11 Prelim Question Paper Solution 5. (a) Let ABC be the binary number and PQRS be the 2s complement output. Input Output A B C P Q R S = C 3/Engg/SE/Pre Pap/23/EXTC/E_Soln

12 : S.E. E P = ABC AB A AC Q = BC B BC R = C C = C S = A B C 5. (b) (i) ecimal to Hexadecimal (237) = (E) E (6) = (258) 6 ecimal to Octal : (237) = (355) 8 (6) = (3) 8 ecimal to BC (237) 2 = () (6) = 6 = () 3 = () = () 7 = () BC (6) = ( ) BC P Q R S 2 3/Engg/SE/Pre Pap/23/EXTC/E_Soln

13 Prelim Question Paper Solution 6. (a) ecimal to Binary : ( ) 2 ( ) 2 (ii) F (A, B, C, ) = m (,, 2, 3, 4, 5, 7, 8, 9,, 4) AB C f ( A, B, C, ) = ABC AC A AB BC B ifference between CPLs & FPGAs CPLs FPGAs Architecture Large, wide fan-in blocks of AN-OR logic Array of small logic blocks surrounded by I/O Applications Bus interfaces complex state machines fast memory interfaces wide decoders PAL-device integration Logic consolidation board integration replace obsolete devices simple state machines complex controllers / interfaces Key Attributes Fast pin-to-pin performance Predictable timing Easy to use Very high density lots of I/Os and flip-flops generally lower power SRAM devices are reprogrammable. Gate Capacity 3-6, gates 8-, gates esign Timing Fixed, PAL-like very fast pinto-pin performance Application dependent very high shift frequencies Number of I/Os /Engg/SE/Pre Pap/23/EXTC/E_Soln 3

14 : S.E. E 6. (b) Number of Flip-flops Process Technology In-System Programmable One-Time Programmable (OTP) Power Consumption CPLs ,5 EPROM EEPROM FLASH Some EEPROM- and FLASH-based devices EPROM devices in plastic packages. Some EEPROMand FLASH-based devices.5-2.w static.5-4.w dynamic FPGAs SRAM Anti-fuse EEPROM SRAM-based devices and some EEPROM-based devices All anti-fuse-based devices Very low static dynamic consumption is application dependent,.-2w typical ABC + AB + ABC + C + B = ABC + ABC + C + B ( + A) ( A + A B = A + B) = ABC + ABC + C + B ( + A) = ABC + ABC + C + B + BA = AB (C + ) + ABC + C + B ( + A = ) = AB + ABC + C + B = B (A + AC ) + C + B ( A + AB = A + B) = B (A + C ) + C + B = AB + BC + C + B Now consider C + B is of form AB + AC also we have identify AB + A C + BC = AB + AC. Thus in above equation A =, B = C and C = B. Thus value C + B remains unchanged if BC is added to it. i.e. C + B + BC = C + B = AB + BC + C + B + BC = AB + B (C + C ) + C + B ( A + A = ) = AB + B + C + B = B ( + A) + C + B ( + A = ) = B + C + B = B ( + ) + C ( + A = ) = B + C ABC + AB + ABC + C + B = B + C 4 3/Engg/SE/Pre Pap/23/EXTC/E_Soln

Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution

Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution . (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)