Digital Integrated Circuits A Design Perspective

Transcription

1 rithmetic ircuitsss dapted from hapter 11 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 Generic Digital Processor MEMORY INPUT-OUTPUT ONTROL DTPTH 2

2 uilding locks for Digital rchitectures rithmetic unit - it-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RM, ROM, uffers, hift registers ontrol - Finite state machine (PL, random logic.) - ounters Interconnect - witches -rbiters -us 3 n Intel Microprocessor 9-1 Mux 5-1 Mux a g64 RRYGEN node1 ck1 UMEL REG sum sumb to ache 9-1 Mux 2-1 Mux b UMGEN + LU s0 s1 LU : Logical Unit 1000um Itanium has 6 integer execution units like this 4

3 it-liced Design ontrol it 3 Data-In Register dder hifter Multiplexer it 2 it 1 it 0 Data-Out Tile identical processing elements 5 it-liced Datapath From register files / ache / ypass Multiplexers hifter dder stage 1 Loopback us Loopback us Wiring dder stage 2 Wiring Loopback us it slice 63 dder stage 3 um elect it slice 2 it slice 1 it slice 0 To register files / ache 6

4 Itanium Integer Datapath Fetzer, Orton, I 02 7 dders 8

5 Full-dder in Full adder um out 9 The inary dder in Full adder um out = = o =

6 Express um and arry as a function of P, G, D Define 3 new variable which ONLY depend on, Generate (G) = Propagate (P) = Delete = an also derive expressions for and o based on D and P Note that we will be sometimes using an alternate definition for Propagate (P) = + 11 The Ripple-arry dder ,0 o,0 o,1 o,2 o,3 F F F F (=,1 ) Worst case delay linear with the number of bits t d = O(N) t adder = (N-1)t carry + t sum Goal: Make the fastest possible carry path circuit 12

7 omplimentary tatic MO Full dder X o 28 Transistors 13 Inversion Property F o F o 14

8 Minimize ritical Path by Reducing Inverting tages Even cell Odd cell ,0 o,0 o,1 o,2 o,3 F F F F Exploit Inversion Property 15 etter tructure: The Mirror dder "0"-Propagate Kill o "1"-Propagate Generate 24 transistors 16

9 Mirror dder tick Diagram o o GND 17 The Mirror dder The NMO and PMO chains are completely symmetrical. maximum of two series transistors can be observed in the carrygeneration circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node o. The reduction of the diffusion capacitances is particularly important. The capacitance at node o is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. The transistors connected to are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. ll transistors in the sum stage can be minimal size. 18

10 Transmission Gate Full dder P P P um Generation P P P o arry Generation etup P 19 Manchester arry hain P i φ P i o G i i o G i P i D i φ 20

11 Manchester arry hain φ P 0 P 1 P 2 P 3 3,0 G 0 G 1 G 2 G 3 φ Manchester arry hain tick Diagram Propagate/Generate Row P i G i φ P i + 1 G i + 1 φ GND Inverter/um Row 22

12 arry-ypass dder,0 P 0 G 1 P 0 G 1 P 2 G 2 P 3 G 3 o,0 o,1 o,2 F F F F o,3 lso called arry-kip P 0 G 1 P 0 G 1 P 2 G 2 P 3 G 3 P=P o P 1 P 2 P 3,0 o,0 o,1 o,2 F F F F Multiplexer o,3 Idea: If (P0 and P1 and P2 and P3 = 1) then o3 = 0, else kill or generate. 23 arry-ypass dder (cont.) it 0 3 etup t setup it 4 7 etup t bypass it 8 11 etup it etup arry propagation arry propagation arry propagation arry propagation um um um t sum um M bits t adder = t setup + M tcarry + (N/M-1)t bypass + (M-1)t carry + t sum 24

13 arry Ripple versus arry ypass t p ripple adder bypass adder 4..8 N 25 arry-elect dder etup P,G "0" "0" arry Propagation "1" "1" arry Propagation o,k-1 Multiplexer o,k+3 um Generation arry Vector 26

14 arry elect dder: ritical Path it 0 3 it 4 7 it 8 11 it etup etup etup etup 0 0-arry 0 0-arry 0 0-arry 0 0-arry 1 1-arry 1 1-arry 1 1-arry 1 1-arry Multiplexer Multiplexer Multiplexer Multiplexer,0 o,3 o,7 o,11 o,15 um Generation um Generation um Generation um Generation t adder = t setup + M tcarry + (N/M)t mux + t sum 27 Linear arry elect it 0-3 it 4-7 it 8-11 it etup etup etup etup (1) "0" (1) "0" arry "0" "0" arry "0" "0" arry "0" "0" arry "1" arry "1" (5) (5) Multiplexer,0 "1" arry "1" arry "1" arry "1" "1" "1" (5) (5) (5) (6) (7) (8) Multiplexer Multiplexer Multiplexer (9) um Generation um Generation um Generation um Generation (10) 28

15 quare Root arry elect it 0-1 it 2-4 it 5-8 it 9-13 it etup etup etup etup (1) "0" "0" arry "0" "0" arry "0" "0" arry "0" "0" arry (1) "1" "1" arry "1" "1" arry "1" "1" arry "1" "1" arry (3) (3) (4) (5) (6) (4) (5) (6) (7) Multiplexer Multiplexer Multiplexer Multiplexer,0 um Generation um Generation um Generation um Generation (7) Mux (8) um (9) t adder = t setup + M tcarry + ( 2N)t mux + t sum 29 dder Delays - omparison 50 t p (in unit delays) Ripple adder Linear select quare root select N 60 30

16 Lookhead - asic Idea o k, = f ( k, k, o k ) = G k + P k ok 1, 1 Expanding Lookahead equations:, ok, = G k + P k ( G k 1 + P k 1 ok, 2 ) ll the way: o k, = G k + P k ( G k 1 + P k 1 ( + P 1 ( G 0 + P 0 0, ))) 0, 0 1, 1 N-1, N-1,0 P 0,1 P 1, N-1 P N N-1 31 Look-head: Topology o k, = G k + P k ( G k 1 + P k 1 ( + P 1 ( G 0 + P 0 0, ))) G 3 G 2 G 1 G 0,0 o,3 P 0 P 1 P 2 P 3 Large fan-in makes it prohibitively slow for lager values of N 32

17 Logarithmic Look-head dder 0 F t p N F t p log 2 (N) 33 arry Lookahead Trees o, 0 = G 0 + P 0, 0 o1, = G 1 + P 1 G 0 + P 1 P 0 0, o2 = G, 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0, 0 = ( G 2 + P 2 G 1 ) + ( P 2 P 1 )( G 0 + P 0 0 ) = G 2:1 + P 2:1 o 0 an continue building the tree hierarchically. (G,P ) (G,P ) where (G,P) G = G + P G P = P P,, 34

18 Tree dders ( 0, 0 ) ( 1, 1 ) ( 2, 2 ) ( 3, 3 ) ( 4, 4 ) ( 5, 5 ) ( 6, 6 ) ( 7, 7 ) ( 8, 8 ) ( 9, 9 ) ( 10, 10 ) ( 11, 11 ) ( 12, 12 ) ( 13, 13 ) ( 14, 14 ) ( 15, 15 ) bit radix-2 Kogge-tone tree 35 Example: Domino dder lk G i = a i b i lk P i = a i + b i a i a i b i b i lk lk Propagate Generate 36

19 Example: Domino dder lk k P i:i-2k+1 lk k G i:i-2k+1 P i:i-k+1 P i:i-k+1 G i:i-k+1 P i-k:i-2k+1 G i-k:i-2k+1 Propagate Generate 37 Multipliers 38

20 The inary Multiplication Z M+ N 1 X = Y = Z k 2 k k = 0 M 1 X i 2 i N 1 Y j 2 j = i = 0 j = 0 = M 1 i = 0 N 1 j = 0 X i Y j 2 i+ j with X Y = = M 1 X i 2 i i = 0 N 1 Y j 2 j j = 0 39 The inary Multiplication + x Multiplicand Multiplier Partial products Result 40

21 The rray Multiplier X 3 X 2 X 1 X 0 Y 0 X 3 X 2 X 1 X 0 Y 1 Z 0 H F F H X3 X 2 X 1 X 0 Y 2 Z 1 F F F H X3 X 2 X 1 X 0 Y 3 Z 2 F F F H Z 7 Z 6 Z 5 Z 4 Z 3 41 The MxN rray Multiplier ritical Path H F F H F F F H ritical Path 1 ritical Path 2 ritical Path 1 & 2 F F F H t mult = [(M-1) + (N-2)] t carry + (N-1) t sum + t and 42

22 arry-ave Multiplier H H H H H F F F H F F F H F F H Vector Merging dder t mult = t and + (N-1) t carry + t merge 43 Multiplier Floorplan X 3 X 2 X 1 X 0 Y 0 Y 1 Z 0 H Multiplier ell F Multiplier ell Y 2 Z 1 Vector Merging ell Y 3 Z 2 X and Y signals are broadcasted through the complete array. ( ) Z 7 Z 6 Z 5 Z 4 Z 3 44

23 Wallace-Tree Multiplier Partial products First stage it position (a) (b) econd stage Final adder F (c) H (d) 45 Wallace-Tree Multiplier Partial products x 3 y 3 x 3 y 2 x 2 y 2 x 3 y 1 x 1 y 2 x 3 y 0 x 1 y 1 x 2 y 0 x 0 y 1 x 2 y 3 x1 y 3 x 0 y 3 x 2 y 1 x 0 y 2 x 1 y 0 x 0 y 0 First stage H H econd stage F F F F Final adder z 7 z 6 z 5 z 4 z 3 z 2 z 1 z 0 46

24 Multipliers ummary Optimization Goals Different Vs inary dder Once gain: Identify ritical Path Other possible techniques - Logarithmic versus Linear (Wallace Tree Mult) - Data encoding (ooth) - Pipelining FIRT GLIMPE T YTEM LEVEL OPTIMIZTION 47 hifters 48

25 The inary hifter Right nop Left i i i-1 i-1 it-lice i The arrel hifter 3 3 h h2 1 : Data Wire : ontrol Wire 0 h3 0 h0 h1 h2 h3 rea Dominated by Wiring 50

26 4x4 barrel shifter h0 h1 h2 h3 uffer 51 Logarithmic hifter h1 h1 h2 h2 h4 h

27 0-77 bit Logarithmic hifter 3 Out3 2 Out2 1 Out1 0 Out0 53